i.MX 6ULL
BOOT_MODE0
BOOT_MODE1
BOOT_CFG1[0]
BOOT_CFG1[5]
BOOT_CFG1[6]
BOOT_CFG1[7]
System Overview
20
TIDUEW7 – May 2020
Copyright © 2020, Texas Instruments Incorporated
Integrated Power Supply Reference Design for NXP i.MX 6ULL
2.4.5
BOOT Configuration
This design uses two sets of BOOT configuration switches. BOOT Mode pins are controlled by SW7 DIP
switches that are connected to dedicated BOOT_MODE0 and BOOT_MODE1 input pins of i.MX 6ULL
Processor. Along with these, there are 24 different pins for setting Boot Config which shares pins with
LCD Data. Of these 24 pins, 4 of them are controlled by the 4 DIP Switches of SW6. All of the possible
BOOT options for this design are given in
(SW7) and
(SW6). The connections of the DIP
switches to the processor are shown in
Figure 20. BOOT Mode and Configuration DIP Switches
Table 5. SW7 BOOT Mode Settings
SW7, PIN 1
SW7, PIN 2
BOOT Type
BOOT_MODE[1]
BOOT_MODE[0]
Boot from Fuses
0
0
Serial Download
0
1
Internal BOOT
1
0
Reserved
1
1
(1)
BT_CFG1[0] is used for SD loopback clock selection.
(2)
To select boot device as eMMC, an assembly change must also be performed. See schematic for details.
Table 6. SW6 BOOT Config Settings
SW6, PIN 4
SW6, PIN 3
SW6, PIN 2
SW2, PIN 1
BOOT Device
BOOT_CFG1[7]
BOOT_CFG1[6]
BOOT_CFG1[5]
BOOT_CFG1[0]
(1)
QSPI
0
0
0
x
SD, eSD, SDXC
0
1
0
x
eMMC
(2)
0
1
1
x