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S

CANH

CANL

FAULT

TXD

GND

V

CC

RXD

FAULT

DTO

DTO

Introduction

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1

Introduction

1.1

Overview

Texas Instruments offers a broad portfolio of High Speed (HS) CAN transceivers compatible with the
ISO11898-2 and ISO11898-5 High Speed CAN standards. These include 5V V

CC

only, 3.3V V

CC

only, 5V

V

CC

with IO level shifting and galvanic isolated CAN transceivers. These CAN transceiver families include

product mixes with varying features such as low power standby modes with and without wake up, silent
modes, loop back and diagnostic modes.

The Texas Instruments SN65HVD257 CAN EVM helps designers evaluate the operation and performance
of the SN65HVD257 CAN transceiver. The SN65HVD257 includes many features for functional safety
network implementation such as redundant CAN networks. The SN65HVD257 CAN EVM also provides
PCB footprints for different bus terminations, bus filtering, and protection concepts. The EVM is provided
with two SN65HVD257 devices installed. A separate EVM is available for the other CAN transceivers,
SN65HVD255 CAN EVM, and another EVM uses the galvanic isolated CAN transceiver family (ISO1050).

The SN65HVD257 meets the ISO1189-2 High Speed CAN (Controller Area Network) Physical Layer
standard (transceiver). It is designed as a next-generation CAN for the SN65HVD251 and ISO1050, but
with added features for functional safety networks such as redundant networks. It has very fast loop times
with a wide range of bus loading, allowing for data rates up to 1 megabit per second (Mbps) in long and
highly loaded networks and higher data rates in small networks. The device includes many protection
features to provide device and CAN network robustness. The device has two modes: normal mode and
silent mode, selected on pin 8. The FAULT pin indicates TXD dominant time out, RXD dominant time out,
thermal shut down and under voltage faults.

Figure 1. SN65HVD257 Basic Block Diagram and Pin Out

1.2

Example Using the SN65HVD257 in a Redundant Physical Layer CAN Network
Topology

CAN is designed for standard linear bus topology using 120

Ω

twisted pair cabling. The SN65HVD257

CAN device includes several features that allow use of the CAN physical layer in nonstandard topologies
with only one CAN link layer controller (

μ

P) interface. The SN65HVD257 allows much greater flexibility in

the physical topology of the bus while reducing the digital controller and software costs. The combination
of RXD dominant time out and the FAULT output provides great flexibility, control and monitoring of these
applications.

A simple example of this flexibility is to use two SN65HVD257 devices combined logically in parallel via an
AND gate to build a redundant (parallel) physical layer (cabling and transceivers) CAN network. Adding a
logic XOR with a filter adds automatic detection for a fault where one of the 2 networks goes open
(recessive) in addition to the faults detected by the SN65HVD257.

To allow CAN’s bit-wise arbitration to work, the RXD outputs of the transceivers must be connected via
AND gate logic so that the link layer logic (

μ

P) receives a dominant bit (low) from any of the branches; the

transceivers appear to the link layer and above as a single physical network. The RXD dominant time out
(DTO) feature prevents a bus stuck dominant fault in a single branch from taking down the entire network
by returning the RXD pin for the transceivers on the branch with the fault to the recessive state (high) after

2

SN65HVD257 CAN EVM: Functional Safety and Redundant CAN Network

SLLU172 – August 2012

Submit Documentation Feedback

Copyright © 2012, Texas Instruments Incorporated

Summary of Contents for SN65HVD257

Page 1: ...d Filtering Configuration 10 3 4 Using Customer Installable IO Options for Current Limiting Pull up or down Noise Filtering 11 3 5 Using customer installable IO options for 3 3V IO 11 4 SN65HVD257 EVM...

Page 2: ...odes normal mode and silent mode selected on pin 8 The FAULT pin indicates TXD dominant time out RXD dominant time out thermal shut down and under voltage faults Figure 1 SN65HVD257 Basic Block Diagra...

Page 3: ...combine the RXD outputs of both branches During dominant bits low were the branches do not match the XOR the circuit outputs a logic high A small RC filter on the output eliminates false outputs due t...

Page 4: ...such as GND VCC TXD RXD CANH CANL S FAULT The EVM supports many options for CAN bus configuration It is pre configured with two 120 resistors that may be connected on the bus via jumpers a single resi...

Page 5: ...5 GND 1 TP8 RXD 1 TP1 GND 1 C17 DNI U1 SN65HVD257 TXD 1 GND 2 Vcc 3 RXD 4 FLT 5 CANL 6 CANH 7 S 8 C13 1uF R10 DNI R17 0 U5 SN65HVD257 TXD 1 GND 2 Vcc 3 RXD 4 FLT 5 CANL 6 CANH 7 S 8 R19 330 C1 DNI TP7...

Page 6: ...60 load for CAN transceiver parametric measurement JMP10 4 pin header Connection for access to transceiver 2 CAN bus output CANH2 CANL2 GND GND Connect 120 CAN termination to the bus Used in combinat...

Page 7: ...XDprime RXD Receive Data 7 GND GND 8 VCC Pin 3 of Transceiver VCC 9 S2 Pin 5 of Transceiver 2 Used for Mode control 10 FLT2 Pin 8 of Transceiver 2 Indicates fault with transceiver 2 11 GND GND 12 FLT3...

Page 8: ...MP1 and TP10 This output indicates a RXD DTO TXD DTO Thermal Shut Down or undervoltage fault with transceiver 1 3 1 7 FLT 2 FAULT pin 5 transceiver 2 JMP1 TP23 Pin 5 of transceiver 2 is the fault outp...

Page 9: ...y the split capacitance is in the range of 4 7nF to 100nF Keep in mind that this is the common mode filter frequency not a differential filter that will impact the differential CAN signal directly Tab...

Page 10: ...us filter environment Filter caps may be used in combination with L1 CM choke To add extra protection for system level transients and ESD protection use the D1 and D2 Transient Protection Transient ES...

Page 11: ...ode pin input from JMP1 or PU or S U1 Input R1 JMP2 R2 NA C1 JMP2 PD to S U1 R27 S Mode pin input from JMP1 or PU or S U2 Input R25 JMP2 R26 NA C21 JMP2 PD to S U2 FAULT3 is the combined RXD output fr...

Page 12: ...r 1 JMP3 may be used to route these signals to an external host processor or test system Make sure that the MODE JMP2 jumper settings are not conflicting with signals to JMP3 JMP2 transceiver 1 config...

Page 13: ...nsceiver 2 Ensure JMP7 and JMP8 are not configured to conflict if TP19 is used as the input connection 4 2 4 FLT2 Output JMP7 TP23 Pin 5 of transceiver 2 is the fault output of the transceiver This ou...

Page 14: ...2 JMP5 JMP10 Header 1x4 HDR_THVT_1X4_100 ANY ACT45B or B82789 series 17 2 L1 L2 DNI TDK EPCOS CM choke 18 4 R1 R16 R25 R40 4 7k 805 ANY R2 R3 R8 R15 R17 R20 R21 R26 19 11 0 805 ANY R27 R32 R39 20 4 R3...

Page 15: ...o handling the product This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI a...

Page 16: ...egulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided...

Page 17: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments SN65HVD257EVM...

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