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7.14.3 EMAC Electrical Data/Timing
7.14.3.1
EMAC MII and GMII Electrical Data/Timing
MRCLK
(Input)
2
3
1
4
4
MTCLK
(Input)
2
3
1
4
4
SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
Table 7-75. Timing Requirements for MRCLK - MII and GMII Operation (see
Figure 7-59
)
-720
-850
A-1000/-1000
-1200
NO.
UNIT
1000 Mbps
100 Mbps
10 Mbps
(GMII Only)
MIN
MAX
MIN
MAX
MIN
MAX
1
t
c(MRCLK)
Cycle time, MRCLK
8
40
400
ns
2
t
w(MRCLKH)
Pulse duration, MRCLK high
2.8
14
140
ns
3
t
w(MRCLKL)
Pulse duration, MRCLK low
2.8
14
140
ns
4
t
t(MRCLK)
Transition time, MRCLK
1
3
3
ns
Figure 7-59. MRCLK Timing (EMAC – Receive) [MII and GMII Operation]
Table 7-76. Timing Requirements for MTCLK - MII and GMII Operation (see
Figure 7-60
)
-720
-850
A-1000/-1000
NO.
UNIT
-1200
100 Mbps
10 Mbps
MIN
MAX
MIN
MAX
1
t
c(MTCLK)
Cycle time, MTCLK
40
400
ns
2
t
w(MTCLKH)
Pulse duration, MTCLK high
14
140
ns
3
t
w(MTCLKL)
Pulse duration, MTCLK low
14
140
ns
4
t
t(MTCLK)
Transition time, MTCLK
3
3
ns
Figure 7-60. MTCLK Timing (EMAC – Transmit) [MII and GMII Operation]
C64x+ Peripheral Information and Electrical Specifications
208
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