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HCS
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE
(A)
HD[15:0]
HRDY
(B)
34
5
17
18
17
18
34
5
4
38
37
13
16
15
14
13
16
15
37
35
SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
A.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B.
Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed
information on the HPI peripheral, see the
TMS320C645x DSP Host Port Interface (HPI) User's Guide
(literature
number
SPRU969
).
Figure 7-46. HPI16 Write Timing (HAS Not Used, Tied High)
C64x+ Peripheral Information and Electrical Specifications
184
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