Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Functional Description
The sensor core receives the SR_CLK sampling clock and the voltage to be sensed. It generates sensor
value samples proportional to the voltage sensed. For accuracy, a sensor core is composed of two
sensors and generates two values per sample (one from each sensor).
The two sample values generated by the sensor core output can be read from the SRn. SENVAL [15:0]
SENNVAL bit field and the SRn. SENVAL [31:16] SENPVAL bit field.
The sensor core is enabled by the SRn. SRCONFIG [10] SENENABLE bit.
Accumulator
The accumulator consists of two stacks that store multiple samples of the two sensor values received from
the sensor core.
The SRn. SRCONFIG [31:22] ACCUMDATA bit field defines the size of the accumulator in the number of
samples to be stored. The allowable range is from 2 to 1023. The SRn. SRCONFIG [31:22] ACCUMDATA
value is related to the desired sampling time window (T
TimeWindow
) and the SR_CLK frequency (f
SR_CLK
). It
can be calculated using Equation 2 :
SRn.SRCONFIG[31:22] ACCUMDATA = T
TimeWindow
* f SR_CLK (2)
For example, for an accumulator time window of 10 ms and SR_CLK frequency of 32 kHz, the
SRn.
SRCONFIG [31:22] ACCUMDATA value is 320 (0x140). The accumulation window must be large
enough so that the minimum, maximum, and average counter values are accurate.
Minimum/Maximum/Average
The minimum/maximum/average block reads the samples stored in the accumulator and returns the
minimum, maximum, and average values of the samples. Because the accumulator contains two separate
groups of samples (one from each sensor of the sensor core), the minimum/maximum/average block also
generates two sets of minimum, maximum, and average values.
The minimum, maximum, and average values of the samples of the first sensor can be read from the
SRn.
SENMIN [15:0] SENNMIN, SRn. SENMAX [15:0] SENNMAX, and SRn. SENAVG [15:0] SENNAVG bit
fields.
For the sample values of the second sensor, the minimum, maximum, and average values can be read
from the SRn.
SENMIN [31:16] SENPMIN, SRn. SENMAX [31:16] SENPMAX, and SRn. SENAVG [31:16]
SENPAVG bit fields.
The minimum/maximum/average block is enabled by the SRn. SRCONFIG [8] MINMAXAVGENABLE bit.
Error Generator
The error-generator block reads the sample value generated by the sensor core and compares it with a
reference value to calculate the error. This error is then passed to the voltage processor and the internal
interrupt generator block.
The reference value for a given OPP of the device is configured by setting the
SRn.
NVALUERECIPROCAL [23:20] SENPGAIN, SRn. NVALUERECIPROCAL [19:16] SENNGAIN,
SRn. NVALUERECIPROCAL [15:8] RNSENP, and SRn. NVALUERECIPROCAL [7:0] RNSENN bit fields by
reading corresponding values from the eFuses (see Section 3.5.6.5.4.5 , eFuse Values).
The error generator sets the SRn. SRSTATUS [1] ERRGEN_VALID status bit when a valid error value is
set in the SRn. SENERROR_REG register.
The SRn. SENERROR_REG register contains the average error (SRn. SENERROR_REG [15:8]
AVGERROR) and the percentage of error (SRn. SENERROR_REG [7:0] SENERROR).
The error generator block is enabled by the SRn. SRCONFIG [9] ERRORGENERATORENABLE bit.
Interrupt Generator
The interrupt generator block generates interrupts to the MPU INTC and the voltage processor module (if
the corresponding interrupts are enabled) to indicate errors.
Table 3-84 and Table 3-85 list the interrupt sources in the SmartReflex module and their enable and
status bits.
383 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated