Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Functional Description
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Table 3-84. SmartReflex Interrupts
Interrupt Type Destination Description
Accumulator MPU INTC The minimum/maximum/average module has completed computation over
the accumulator data.
Valid MPU INTC The average error is less than 2 percent of the true average error.
Disable acknowledge MPU INTC The SmartReflex module is disabled and has cleared all MCU and VP
interrupts (internal registers are reset). This interrupt indicates to the
software that the SmartReflex module is available for programming.
Bounds MPU INTC The frequency error has crossed the maximum limit (ERRMAXLIMIT) or
the minimum limit (ERRMINLIMIT).
Voltage processor
The interrupt mappings to the MPU INTC are:
• SR1_IRQ from the SmartReflex1 module to the M_IRQ_18 interrupt line of the MPU INTC
• SR2_IRQ from the SmartReflex2 module to the M_IRQ_19 interrupt line of the MPU INTC
Table 3-85. SmartReflex Interrupt Enable and Status Bits
Interrupt Type Enable Bit Status Bit
Accumulator SRn. IRQENABLE_SET [3] SRn. IRQSTATUS [3]
MCUACCUMINTENASET MCUACCUMINTSTATENA
Valid SRn. IRQENABLE_SET [2] SRn. IRQSTATUS [2]
MCUVALIDINTENASET MCUVALIDINTSTATENA
Disable acknowledge SRn. IRQENABLE_SET [0] SRn. IRQSTATUS [0]
MCUDISABLEACTINTENASET MCUDISABLEACKINTSTAT
Bounds SRn. IRQENABLE_SET [1] SRn. IRQSTATUS [1]
MCUBOUNDSINTSTATENA MCUBOUNDSINTENASET
SRn. ERRCONFIG [22] SRn. ERRCONFIG [23]
VPBOUNDSINTENABLE VPBOUNDSINTSTATENA
The minimum and maximum error limits for the bounds interrupt are configured in the
SRn.
ERRCONFIG [15:8] ERRMAXLIMIT and SRn. ERRCONFIG [7:0] ERRMINLIMIT bit fields.
With automatic (hardware) voltage control, the voltage processor interrupt (iSRn. ERRCONFIG [22]
VPBOUNDSINTENABLE) is enabled and the SmartReflex module interrupts the voltage processor module
when the error crosses the error limits. In this case, the MPU interrupts can also be enabled to allow the
software to monitor the SmartReflex module behavior.
With manual (software) voltage control, the voltage processor interrupt remains disabled and only the
MPU interrupts are enabled. Thus, when an interrupt condition occurs, the MPU is interrupted and the
software can then control the voltage by generating voltage commands.
Writing 1 to a bit in the IRQSTATUS register clears the interrupt pending status of each interrupt source
whose corresponding bit is 1 in the value written. Other interrupt pending status bits are not affected
(writing 0 to that bit does not affect the status).
3.5.6.5.4.4 Status Register
The status register ( SRSTATUS ) indicates the validity of the minimum/maximum/average and
error-generator output values.
SRSTATUS has the following bits and bit fields:
• SRn. SRSTATUS [3] AVGERRVALID: Indicates the validity of the value in the
SRn. SENERROR_REG [15:8] AVGERROR bit field. When the value is 0, the average error is not valid.
When the value is 1, the average error is within 2 percent of the valid average error.
• SRn. SRSTATUS [2] MINMAXAVGVALID: Indicates the validity of the SRn. SENVAL , SRn. SENMIN ,
SRn. SENMAX , and SRn. SENAVG registers. When the value is 0, the registers are not valid. When the
value is 1, the registers contain valid values, although the values are not necessarily fully accumulated.
• SRn. SRSTATUS [1] ERRGEN_VALID: Indicates the validity of the value in the
384 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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