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McBSP Integration
NOTE:
When the McBSP5 module does not require the interface clock anymore, the software can
disable it at the PRCM level by setting the EN_MCBSP5 bit
(PRCM.CM_ICLKEN1_CORE[10]) in the PRCM registers. The clock is effectively cut,
provided the other modules that receive it do not require it. For more information, see
, Power Reset and Clock Management.
At PRCM level, when all the conditions to shut-off CORE_L4_ICLK clock are met the PRCM
automatically launches a hardware handshake protocol to ensure McBSP5 is ready to have
this clock switched off. Namely, the PRCM asserts an idle request to McBSP5. For more
details, see
, Power Reset and Clock Management.
It is also possible to activate an autoidle mode for this clock
(PRCM.CM_AUTOIDLE1_CORE[10] register AUTO_MCBSP5 bit set to 1). In this case,
McBSP5_ICLK follows the CORE_L4 clock domain behavior on the device. For more
information, see
, Power Reset and Clock Management.
21.3.2.2.6 SIDETONE Clock
The SIDETONE feature, in the McBSP2 and McBSP3 modules, is clocked only by an interface clock
(McBSP2_ICLK or McBSP3_ICLK).
CAUTION
See
and
for
information
on
McBSP2_ICLK and McBSP3_ICLK clocks.
When the SIDETONE feature does not require the clock anymore, the software can disable it at the
SIDETONE level by setting the McBSPi.
[0] AUTOIDLE bit in SIDETONE registers.
To conserve power, when SIDETONE feature is not active or there is no activity on SIDETONE feature,
the McBSPi_ICLK clock supports an automatic gating that is enabled or disabled by setting the
McBSPi.
[0] AUTOIDLE bit.
•
When this bit is asserted (set to 1), the McBSPi_ICLK clock auto-gating is enabled and this clock is
disabled internally to the SIDETONE feature, thus reducing power consumption, but not to the McBSP
module that contains this feature.
After reset, the automatic clock gating is enabled; thus, this bit must be disabled by software for
activated SIDETONE feature.
•
When this bit is set to 0, the McBSPi_ICLK clock auto-gating is disabled and this clock is enabled. The
SIDETONE feature can be used normally.
21.3.2.3 Hardware and Software Reset
McBSP1 and McBSP5 modules belong to the CORE domain and their reset signal is the CORE_RST
signal from the PRCM module, whereas McBSP2, 3 and 4 modules belong to the PER domain and their
reset signal is the PER_RST signal from the PRCM module.
For more details about these signals, see
, Power Reset and Clock Management.
Table 21-4. Software Reset Signals to All McBSP Modules
Type
Bit Field
Register Source
Activation
Description
Software
SOFTRESET
MCBSPi.
Active high
McBSP global software reset
RRST
MCBSPi.
[0]
Active low
This resets and disables the receiver,
including the RB.
XRST
MCBSPi.
[0]
This resets and disables the
transmitter, including the XB.
GRST
MCBSPi.
[6]
SRG is reset
3079
SWPU177N – December 2009 – Revised November 2010
Multi-Channel Buffered Serial Port
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