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McBSP Integration
–
0: The CLKS source is from the CORE_96M_FCLK.
–
1: The CLKS source is from the mcbsp_clks pin.
For more information on this register , see
, System Control Module.
NOTE:
When the McBSP1 module does not require the PRCM functional clock anymore, the
software can disable it at the PRCM level by setting the EN_MCBSP1 bit
(PRCM.CM_FCLKEN1_CORE[9]) in the PRCM registers. The clock is effectively cut,
provided the other modules that receive it do not require it. For more details, see
Power Reset and Clock Management.
At PRCM level, when all the conditions to shut-off CORE_96M_FCLK clock are met the
PRCM automatically launches a Hardware handshake protocol to ensure McBSP1 is ready
to have this clock switched off. Namely, the PRCM asserts an idle request to McBSP1. For
more details, see
, Power Reset and Clock Management.
The CLKX and CLKR signals are connected either by mcbsp1_clkx or mcbsp1_clkr pads. These
signals are used like functional clocks by the intermediary of the sample rate generator (SRG).
•
The McBSP1_ICLK runs at the L4 core interconnect clock speed. It is used to trigger access to the
McBSP1 L4 interface and McBSP1 configuration interface via the MPU/IVA2.2 shared bus. It can also
be an input clock for the McBSP sample-rate generator (clock divider), depending on the module
configuration (see
). Its source is the CORE_L4_ICLK signal.
NOTE:
When the McBSP1 module does not require the interface clock anymore, the software can
disable it at the PRCM level by setting the EN_MCBSP1 bit (PRCM.CM_ICLKEN1_CORE[9])
in the PRCM registers. The clock is effectively cut, provided the other modules that receive it
do not require it. For more information, see
, Power Reset and Clock Management.
At PRCM level, when all the conditions to shut-off CORE_L4_ICLK clock are met the PRCM
automatically launches a hardware handshake protocol to ensure McBSP1 is ready to have
this clock switched off. Namely, the PRCM asserts an idle request to McBSP1. For more
details, see
, Power Reset and Clock Management.
It is also possible to activate an autoidle mode for this clock
(PRCM.CM_AUTOIDLE1_CORE[9] register AUTO_MCBSP1 bit set to 1). In this case,
McBSP1_ICLK follows the CORE_L4 clock domain behavior on the device. For more
information, see
, Power Reset and Clock Management.
21.3.2.2.2 McBSP2 Clocks
The McBSP2 module is clocked by a functional clock (CLKS, CLKX or CLKR) and an interface clock
(McBSP2_ICLK).
•
The functional clock is used to generate control signals depending on the module internal configuration
(see
). For McBSP2 module, the functional clock comes from the CLKS signal CLKX
signal, or CLKR signal. The choice between these three clocks is defined by the SCLKME bit of the
MCBSP2.
[7] register and the CLKSM bit of the
[13] register.
The CLKS signal of the McBSP2 module is linked to an internal clock (PER_96M_FCLK) provided by
PRCM, whereas the CLKS signal can also be linked to an external signal through the mcbsp_clks pin
of the device boundary. The MCBSP2_CLKS bit of the CONTROL.CONTROL_DEVCONF0[6] register
is used to select the McBSP2 module CLKS signal source:
–
0: The CLKS source is from the PER_96M_FCLK.
–
1: The CLKS source is from the mcbsp_clks pin.
For more information, see
, System Control Module.
3075
SWPU177N – December 2009 – Revised November 2010
Multi-Channel Buffered Serial Port
Copyright © 2009–2010, Texas Instruments Incorporated