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IPC Mailbox Register Manual
Table 14-15. Register Call Summary for Register MAILBOX_MSGSTATUS_m
IPC Mailbox Functional Description
•
•
•
IPC Mailbox Basic Programming Model
•
Mailbox Communication Preparation
:
•
Mailbox Communication Sequence
:
[7] [8] [9] [10] [11] [12] [13]
•
Sending a Message (Interrupt Method)
IPC Mailbox Register Manual
•
Mailbox Register Mapping Summary
Table 14-16. MAILBOX_IRQSTATUS_u
Address Offset
0x100 = MAILBOX_IRQSTATUS_0 for user 0
0x108 = MAILBOX_IRQSTATUS_1 for user 1
Physical Address
0x4809 4100 = MAILBOX_IRQSTATUS_0 for user 0
Instance
MLB
0x4809 4108 = MAILBOX_IRQSTATUS_1 for user 1
Description
The interrupt status register has the status for each event that may be responsible for the generation of an
interrupt to the corresponding user - write 1 to a given bit resets this bit
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
NOTFULLSTATUSUUMB1
NOTFULLSTATUSUUMB0
NEWMSGSTATUSUUMB1
NEWMSGSTATUSUUMB0
Bits
Field Name
Description
Type
Reset
31:4
Reserved
Write 0s for future compatibility Read returns 0
RW
0x0000000
3
NOTFULLSTATUSUUMB1
NotFull Status bit for User u, Mailbox 1
RW
0
2
NEWMSGSTATUSUUMB1
NewMessage Status bit for User u, Mailbox 1
RW
0
1
NOTFULLSTATUSUUMB0
NotFull Status bit for User u, Mailbox 0
RW
0
0
NEWMSGSTATUSUUMB0
NewMessage Status bit for User u, Mailbox 0
RW
0
Table 14-17. Register Call Summary for Register MAILBOX_IRQSTATUS_u
IPC Mailbox Functional Description
•
IPC Mailbox Functional Description
:
•
IPC Mailbox Basic Programming Model
•
Mailbox Communication Preparation
:
•
Mailbox Communication Sequence
:
IPC Mailbox Register Manual
•
Mailbox Register Mapping Summary
2661
SWPU177N – December 2009 – Revised November 2010
Interprocessor Communication
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