Public Version
IPC Mailbox Functional Description
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14.3.4 16-Bit Register Access
14.3.4.1 Description
So that 16-bit processors can access the mailbox module, the device allows 16-bit register read and write
access, with restrictions for the MAILBOX.
registers. The 16-bit half-words are
organized in little endian fashion; that is, the least-significant 16 bits are at the low address and the
most-significant 16 bits are at the high address (low a 0x02).
All mailbox module registers can be read or written to directly using individual 16-bit accesses with no
restriction on interleaving, except the MAILBOX.
registers, which must always be
accessed by either single 32-bit accesses or two consecutive 16-bit accesses.
CAUTION
When using 16-bit accesses, it is critical to ensure that the mailbox used has
only one assigned receiver and only one assigned sender.
When using 16-bit accesses to the MAILBOX.
registers, the order of access
must be the least-significant half-word first (low address) and the most-significant half-word last (high
address). This requirement is due to the update operation by the message FIFO of the
MAILBOX.
registers. The update of the FIFO queue contents and the
associated status registers and possible interrupt generation occurs only when the most-significant 16 bits
of a MAILBOX.
are accessed.
2652
Interprocessor Communication
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
