Texas Instruments OMAP36 Series, Technical Reference Manual

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IPC Mailbox Basic Programming Model
14.4 IPC Mailbox Basic Programming Model
14.4.1 Initialization Flow for the Mailbox Module
The initialization flow for the mailbox module consists of the following steps:
1. Perform a software reset of the mailbox module (see Section 14.4.1.1 , Software Reset).
2. Set the idle mode and clock configuration of the mailbox module (see Section 14.4.1.2 , Idle Mode and
Clock Configuration).
14.4.1.1 Software Reset
To perform a software reset, write 1 in the MAILBOX. MAILBOX_SYSCONFIG [1] SOFTRESET bit. The
MAILBOX. MAILBOX_SYSSTATUS [0] RESETDONE bit indicates that the software reset is complete when
its value is 1.
When the software reset completes, the MAILBOX. MAILBOX_SYSCONFIG [1] SOFTRESET bit is
automatically reset. The software must ensure that the software reset completes before doing mailbox
operations.
CAUTION
When performing a software reset by writing 1 in the MAILBOX.
MAILBOX_SYSCONFIG [1] SOFTRESET bit, 0 must be written in the other bits
of the MAILBOX. MAILBOX_SYSCONFIG register.
14.4.1.2 Idle Mode and Clock Configuration
The idle mode and clock configuration is done by setting the MAILBOX. MAILBOX_SYSCONFIG [4:3]
SIDLEMODE field and the MAILBOX. MAILBOX_SYSCONFIG [0] AUTOIDLE bit (see Section 14.5 ,
Mailbox Register Manual, for more information).
14.4.2 Mailbox Assignment
Before communicating, mailboxes can be explicitly assigned to a user using the appropriate
MAILBOX.
MAILBOX_IRQENABLE_u register. The software must ensure that only one sender and one
receiver are assigned per mailbox.
For example, to assign mailbox 1 (m = 1) to the MPU (u = 0, see Section 14.3 , Mailbox Functional
Description, for the user number) as a receiver, set the MAILBOX.MAILBOX_IRQENABLE_0[2]
NEWMSGENABLEUUMB1 bit to generate an interrupt to the MPU when a new message is received in
mailbox 1.
To assign mailbox 0 (m = 0) to the MPU (u = 0) as a sender, set the
MAILBOX.MAILBOX_IRQENABLE_0[1] NOTFULLENABLEUUMB0 bit to generate an interrupt to the
MPU when the message queue of mailbox 0 is not full.
14.4.3 Mailbox Communication Preparation
Before communicating with another user, the sender must first use one of the following methods to
determine that the mailbox message FIFO queue is not full:
• Poll the MAILBOX. MAILBOX_FIFOSTATUS_m [0] FIFOFULLMB bit or the
MAILBOX. MAILBOX_MSGSTATUS_m [2:0] NBOFMSGMB field to determine if there is an open slot
available to write a message.
• If the queue-not-full interrupt is enabled by setting the corresponding bit in the
MAILBOX.
MAILBOX_IRQENABLE_u register, an interrupt to the sender indicates that the mailbox has
an available slot. To avoid continuous interrupt to the sender, it is recommended that the software
waits until the message queue is full by reading the MAILBOX.
MAILBOX_MSGSTATUS_m [2:0]
NBOFMSGMB field before enabling the interrupt in the MAILBOX. MAILBOX_IRQENABLE_u register.
When a queue-not-full interrupt is generated to the sender, the interrupt should be disabled until the
2653 SWPU177N – December 2009 – Revised November 2010 Interprocessor Communication
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