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IPC Mailbox Register Manual
14.5 IPC Mailbox Register Manual
summarizes the mailbox instance.
Table 14-2. Mailbox Instance Summary
Module Name
Base Address
Size
MLB
0x4809 4000
4K bytes
14.5.1 Mailbox Register Mapping Summary
summarizes the MLB registers.
Table 14-3. MLB Register Summary
Register Name
Type
Register Width (Bits)
Address Offset
Physical Address
R
32
0x000
0x4809 4000
RW
32
0x010
0x4809 4010
R
32
0x014
0x4809 4014
(1)
RW
32
0x040 + (0x04 * m)
0x4809 4040 + (0x04 * m)
(1)
R
32
0x080 + (0x04 * m)
0x4809 4080 + (0x04 * m)
(1)
R
32
0x0C0 + (0x04 * m)
0x4809 40C0 + (0x04 * m)
(2)
RW
32
0x100 + (0x08 * u)
0x4809 4100 + (0x08 * u)
(2)
RW
32
0x104 + (0x08 * u)
0x4809 4104 + (0x08 * u)
(1)
m = 0 to 1
(2)
u = 0 to 1
NOTE:
In MAILBOX_MESSAGE_0, MAILBOX_MESSAGE_1, MAILBOX_FIFOSTATUS_0,
MAILBOX_FIFOSTATUS_1, MAILBOX_MSGSTATUS_0, and MAILBOX_MSGSTATUS_1
register names, 0 or 1 is the mailbox number.
In MAILBOX_IRQSTATUS_0, MAILBOX_IRQSTATUS_1, MAILBOX_IRQENABLE_0, and
MAILBOX_IRQENABLE_1 register names, 0 or 1 is the user number:
•
User 0: MPU subsystem
•
User 1: IVA2.2 subsystem
14.5.2 Register Description
through
describe the register bits.
Table 14-4. MAILBOX_REVISION
Address Offset
0x000
Physical Address
0x4809 4000
Instance
MLB
Description
This register contains the IP revision code
Type
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
REV
Bits
Field Name
Description
Type
Reset
31:8
Reserved
Reads returns 0
R
0x000000
7:0
REV
IP revision
R
See
(1)
[7:4] Major revision
[3:0] Minor revision
Examples: 0x10 for 1.0, 0x21 for 2.1
(1)
TI internal data
2657
SWPU177N – December 2009 – Revised November 2010
Interprocessor Communication
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