Public Version
IPC Mailbox Register Manual
www.ti.com
Table 14-5. Register Call Summary for Register MAILBOX_REVISION
IPC Mailbox Register Manual
•
Mailbox Register Mapping Summary
Table 14-6. MAILBOX_SYSCONFIG
Address Offset
0x010
Physical Address
0x4809 4010
Instance
MLB
Description
This register controls the various parameters of the L4-Core interface
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
AUTOIDLE
SIDLEMODE
SOFTRESET
CLOCKACTIVITY
Bits
Field Name
Description
Type
Reset
31:9
Reserved
Write 0's for future compatibility
RW
0x000000
Read returns 0
8
CLOCKACTIVITY
Clock activity during wake up mode period
R
0
Clock can always be switched off and read returns 0
7:5
Reserved
Write 0's for future compatibility
RW
0x0
Read returns 0
4:3
SIDLEMODE
RW
0x0
0x0:
Force-idle. An idle request is acknowledged unconditionally
0x1:
No-idle. An idle request is never acknowledged
0x2:
Smart-idle. Acknowledgement to an idle request is given
based on the internal activity of the module based on the
internal activity of the module
0x3:
Reserved. Do not use.
2
Reserved
Write 0's for future compatibility Read returns 0
RW
0
1
SOFTRESET
Software reset. This bit is automatically reset by the hardware. During
RW
0
reads, it always return 0
0x0:
Normal mode
0x1:
The module is reset
0
AUTOIDLE
Internal interface clock gating strategy
RW
0
0x0:
Interface clock is free-running
0x1:
Automatic interface clock gating strategy is applied, based
on the L4-Core interface activity
Table 14-7. Register Call Summary for Register MAILBOX_SYSCONFIG
IPC Integration
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•
:
IPC Mailbox Basic Programming Model
•
•
Idle Mode and Clock Configuration
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IPC Mailbox Register Manual
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Mailbox Register Mapping Summary
2658Interprocessor Communication
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated