MBOX_IDLEREQ
IVA2_IRQ[10]
Device
L4-Core interconnect
IPC
MAILBOX
MAIL_U1_IVA2_IRQ
MAIL_U0_MPU_IRQ
Mailbox
(x2)
MAILBOX_FCLK
PRCM
CORE_L4_ICLK
MPU subsystem
Interrupt controller
Interrupt controller
M_IRQ_26
MBOX_SIDLEACK
IVA2.2 subsystem
ipc-002
Public Version
www.ti.com
IPC Integration
Figure 14-2. IPC Integration
14.2.1 Clocking, Reset, and Power-Management Scheme
14.2.1.1 Clocks
14.2.1.1.1 Module Clocks
The mailbox module receives one input clock, CORE_L4_ICLK, from the power, reset, and clock
management (PRCM) module. CORE_L4_ICLK is gated internally and can be turned off to lower
operating power when a module is not active. The exact frequency of this clock depends on PRCM
programming.
14.2.1.2 Resets
The IPC supports both a hardware reset and a software reset.
14.2.1.2.1 Hardware Reset
The mailbox module receives its reset signal, CORE_RST (the reset signal of the CORE power domain),
from the PRCM module.
14.2.1.2.2 Software Reset
The mailbox module supports a software reset by accessing the MAILBOX.
[1]
SOFTRESET bit (0: normal mode, 1: module is reset).
14.2.1.3 Power Domains
The mailbox module connects to the CORE power domain.
2647
SWPU177N – December 2009 – Revised November 2010
Interprocessor Communication
Copyright © 2009–2010, Texas Instruments Incorporated
