Texas Instruments OMAP36 Series, Technical Reference Manual

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IPC Mailbox Basic Programming Model
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message queue is full for the same reason.
The receiver can also detect new messages from another user using two methods:
• Poll the MAILBOX. MAILBOX_FIFOSTATUS_m [0] FIFOFULLMB bit or the
MAILBOX. MAILBOX_MSGSTATUS_m [2:0] NBOFMSGMB field.
• Use a new message ISR (interrupt service routine). In this case, the receiver must enable the
appropriate interrupt in the MAILBOX.
MAILBOX_IRQENABLE_u register.
NOTE: After an interrupt is generated, and before exiting the ISR, write 1 in each bit responsible for
this generation in the MAILBOX. MAILBOX_IRQSTATUS_u register, thereby clearing these
bits.
14.4.4 Mailbox Communication Sequence
When a message slot is available in the mailbox, a message can be transmitted by a sender to a receiver
using the following steps:
1. The sender writes a message in the MAILBOX. MAILBOX_MESSAGE_m register. This results in the
following actions:
• The message is stored at the tail of the FIFO queue of mailbox m, and the
MAILBOX.
MAILBOX_FIFOSTATUS_m and MAILBOX. MAILBOX_MSGSTATUS_m registers are
updated.
• If the FIFO queue was previously empty, a new message interrupt can be generated to the
receiver to which the mailbox is allocated; otherwise, the interrupt is already asserted and remains
so.
2. The receiver can either use an ISR or poll the MAILBOX. MAILBOX_FIFOSTATUS_m or
MAILBOX. MAILBOX_MSGSTATUS_m registers to detect new messages and read them by accessing
the MAILBOX. MAILBOX_MESSAGE_m register.
• If using interrupts, the receiver enters the ISR when it detects the new message interrupt. The
receiver checks both the MAILBOX.
MAILBOX_IRQSTATUS_u register to determine the source of
the interrupt and the MAILBOX. MAILBOX_MSGSTATUS_m register(s) to determine the number of
messages in the FIFO queue.
• The receiver can poll the appropriate MAILBOX. MAILBOX_MSGSTATUS_m register(s) to check
the status and determine if there are any pending messages to read. The receiver can read the
MAILBOX.
MAILBOX_MSGSTATUS_m [2:0] NBOFMSGMB field to determine how many messages
are available.
3. Using either ISR or polling method, when the receiver determines that it has a message pending in a
mailbox, it repeatedly reads the MAILBOX. MAILBOX_MESSAGE_m register to remove all messages
from the FIFO queue until a read in the MAILBOX. MAILBOX_MSGSTATUS_m register indicates no
more messages are available (MAILBOX. MAILBOX_MSGSTATUS_m [2:0] NBOFMSGMB field =
0x00).
4. After reading all of the messages, the receiver can acknowledge the new message interrupt by writing
1 in the appropriate bit of the MAILBOX. MAILBOX_IRQSTATUS_u register to clear the interrupt flag
before exiting the ISR.
14.4.5 Example of Communication
This example shows how communication is established between the MPU and IVA2.2 subsystems in the
device. The MPU subsystem sends messages to the IVA2.2 subsystem through mailbox 0, and the IVA2.2
subsystem sends messages to the MPU subsystem through mailbox 1.
To establish communication, the software follows these steps:
1. Turn on the automatic idle feature by writing 1 in the MAILBOX. MAILBOX_SYSCONFIG [0] AUTOIDLE
bit.
2. Configure the mailbox in smart-idle mode by setting the MAILBOX. MAILBOX_SYSCONFIG [4:3]
SIDLEMODE field in smart-idle mode (smart-idle is the recommended mode; see Section 14.5 ,
Mailbox Register Manual, for more information). Smart-idle mode allows the PRCM low-power-mode
requests to be acknowledged only after clearing any pending interrupts.
2654 Interprocessor Communication SWPU177N – December 2009 – Revised November 2010
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