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SDMA Functional Description
11.4.19.4.2 Starting a Linked List
Like a nonlinked-list transfer, a link transfer starts under host control by enabling the associated logical
channel (set the
[7] ENABLE bit to 1). The
[10] FAST bit sets the start mode of
the link-list transfer:
In nonfast-start mode, the logical channel configuration is fully initialized so that the transfer can start
without descriptor loading.
In fast-start mode, the descriptor pointer and other inputs are given. The channel starts by loading the
descriptor and then starts the data transfer phase.
11.4.19.4.3 Monitoring a Linked-List Progression
In addition to the
(remaining elements) and
(remaining frames) registers that
are used to monitor the transfer progress, a per-channel register,
(channel current active
descriptor number), monitors which descriptor in the list is active. The user must initialize the
register to 0 during the initial configuration. When the
register is updated,
the
and the
registers are updated. The user must also initialize the
and
registers to 0xFFFF and to 0xFFFFFF, respectively, to track the
effective transfer start of synchronized transfer.
11.4.19.4.4 Interrupt During Linked-List Execution
Any logical channel source of interrupt can be triggered during a linked-list execution, if the interrupt
source is enabled. during the initial configuration in CICR. The
register can also be updated
during the linked-list execution if descriptor types 1 and 2 are used.
The use of an interrupt event in a link execution can be difficult, because the link can progress in parallel
with interrupt service routine (ISR) execution. This makes it difficult to synchronize them unless system
assumptions are used. The most appropriate synchronization model is to get an interrupt-only on
linked-list completion, when the last transfer block is complete. This prevents the interrupt from occurring
during the link execution. An end-of-super-block interrupt event available in the
and
registers can be enabled at initial configuration or when using descriptor types 1 and 2. To
prevent the use of descriptor type 1 or 2 to update BLOCK_IE (full
update), a dedicated
BLOCK_IE bit field is also available in a type 3 descriptor.
11.4.19.4.5 Pause a Linked List
When the channel is suspended, it remains enabled.
The pause behaves differently, depending on the transfer mode:
•
Normal transfer mode: If the user sets the
[7] PAUSE_LINK_LIST bit to 1, the channel
completes the current read and write transactions and then suspends the channel. The channel can be
resumed by setting the channel
[7] PAUSE_LINK_LIST bit to 0.
•
Linked-list type 1, 2, or 3 mode: The user must not set the
[7] PAUSE_LINK_LIST bit
through the configuration port; otherwise, transfer behavior is undefined.
A PAUSE_LINK_LIST bit (P) is set to 1 in the descriptor.
–
The channel is suspended after the descriptor load, translation, and configuration memory update
are complete.
–
The linked list can be resumed by resetting the
[7] PAUSE_LINK_LIST bit (through the
configuration port).
2365
SWPU177N – December 2009 – Revised November 2010
SDMA
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