Public Version
www.ti.com
SDMA Functional Description
NOTE:
Regardless of whether buffering is enabled or not, buffering is not performed between
frames. If the packed/burst is across the frame boundary, the last packed/burst write
transaction is split into optimized smaller accesses to complete the frame transfer size.
•
Synchronized at the destination
The performance of a hardware-synchronized transfer can be improved by using the prefetch mode,
enabled through the channel DMA register bit
[23]. Data is prefetched on the read port
side in advance of the DMA request received and buffered in the FIFO queue. Up to a full transfer
block can be prefetched, although this can be limited by the specified maximum channel FIFO queue
depth (see
, FIFO Queue Memory Pool).
Buffering disable is not allowed for a destination-synchronized transfer.
NOTE:
Behavior is undefined when prefetch is enabled and a transfer is synchronized to the
source.
Whether buffering is enabled or disabled, the last transaction in the frame or in the block is
write nonposted (WNP) even if the write mode is specified as write last nonposted (WLNP;
the WRITE_MODE bit field of the
register = 0x2). However, in a packet
synchronization mode, the last transaction of each packet in the transfer is WNP only if
buffering disable is on (even if the write mode is specified as WLNP).
Regardless of whether buffering disable is enabled or disabled, the packet interrupt is not
generated in the packet source synchronized mode.
CAUTION
The BUFFERING_DISABLE bit field of the
register must be filled
with an allowed value, as specified in
Table 11-7. Buffering Disable
BUFFERING_DISABLE
(0: buffering enable, 1: buffering disable)
Destination synchronized
0
Allowed
1
Not allowed
Source synchronized
0
Allowed
1
Allowed
Synchronized transfer monitoring using CDAC (
):
Context is restored only when the channel becomes active on a DMA request (not at software enable).
The channel is software-enabled first, and then a DMA request is asserted followed by the first context
restore.
The CDAC register is writable; thus, you can initialize the CDAC to monitor the transfer and determine if
the transfer is started or not (see
, Synchronized Transfer Monitoring Using CDAC, for more
information).
NOTE:
For 16-bit transactions, start reading from or writing to the LSByte first to enable the register
update. This is not an issue for 32-bit read-write transactions.
2355
SWPU177N – December 2009 – Revised November 2010
SDMA
Copyright © 2009–2010, Texas Instruments Incorporated