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SDMA Functional Description
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For a logical channel transfer completion, when the last access is written to the destination, the logical
channel becomes inactive. If enabled, an interrupt request is generated (see
, Interrupt
Generation).
11.4.2 FIFO Queue Memory Pool
A FIFO queue memory pool provides buffering between the read and write ports. The hardware allocates
the space dynamically to a number of FIFO queues, and each queue is associated with an active logical
channel.
To avoid a memory pool overflow, if there are fewer entries in the FIFO queue memory pool than are
required for the maximum configured source burst size of the next logical channel to be scheduled, the
logical channel is returned to the tail of the queue, and the port access scheduler continues to search the
queue until it finds a logical channel that can be scheduled.
The maximum FIFO depth that can be allocated to each individual logical channel can be limited globally
through the
register. This value should be configured to allow a fair allocation of the memory
pool between the active channels.
A logical channel is scheduled if it has not yet reached its allocation limit, even if the access to be
performed will exceed this limit. This means that the effective number of entries used by a particular
logical channel is limited to the configured maximum entries per c channel maximum configured
burst size (in words) -1.
11.4.3 Addressing Modes
A DMA transfer block consists of a number of frames (FN). Each frame consists of a number of elements,
and each element can have a size of 8, 16, or 32 bits, as follows:
transfer block size = number of frames x number of elements per frame x element size
The FN, number of elements per frame (EN), and size of elements are common for both the source and
destination. However, the way in which the data is represented (addressing profile/mode) is independently
programmable for the source and destination devices, using one of these four addressing modes:
•
Constant: The address remains the same for consecutive element accesses.
•
Post-increment: The address increases by the element size (ES), even across consecutive frames.
•
Single-index: The address increases by the ES, plus the element index (EI) value minus one (even
across consecutive frames).
•
Double-index: The address increases by the ES, plus the EI value minus one within a frame. When a
full frame is transferred, the address increases by the ES plus the frame index (FI) value minus 1.
The ES, EI, and FI values are expressed in bytes. The EI and FI values can be positive or negative.
When calculating the EI and FI values, it is critical to note that, after an element is accessed, the logical
channel address pointer equals the address of the last byte (highest address) of the accessed element.
The correct value for the EI or FI should be such that, when added to the logical channel address pointer,
results in the address of the first byte (lowest address) of the next element to be accessed.
The EI and FI values must be configured so that the address of each element in the transfer is aligned on
an ES boundary.
Consequently, the single-index addressing mode with EI = 1 or double-index addressing mode with EI = 1
and FI = 1 is equivalent to post-increment addressing.
NOTE:
The source and destination start addresses must also be aligned on an ES boundary.
When the address of an element to be accessed is not aligned on an ES boundary, the transfer is stopped
and a misaligned address error interrupt occurs, if enabled (see
, Interrupt Generation).
The
register configures the FN in a block.
The
register configures the EN.
The
register configures the ES.
2348
SDMA
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated