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SDMA Functional Description
•
When HI_LO_FIFO_BUDGET = 0x1, then low priority cannot exceed 75 percent of the total FIFO.
•
When HI_LO_FIFO_BUDGET = 0x2, then low priority cannot exceed 25 percent of the total FIFO.
•
When HI_LO_FIFO_BUDGET = 0x3, then low priority cannot exceed 50 percent of the total FIFO.
If channel is high priority
•
When HI_LO_FIFO_BUDGET = 0x1, then high priority cannot exceed 25 percent of the total FIFO.
•
When HI_LO_FIFO_BUDGET = 0x2, then high priority cannot exceed 75 percent of the total FIFO.
•
When HI_LO_FIFO_BUDGET = 0x3, then high priority cannot exceed 50 percent of the total FIFO.
The user is responsible for performing the following equation:
•
For a high-priority channel: (Per_Channel_Maximum FIFO Depth + 1) x Number of High Channel =<
High Budget FIFO
•
For a low-priority channel: (Per_Channel_Maximum FIFO Depth + 1) x Number of Low Channel =<
Low Budget FIFO
NOTE:
Ensure that Number of High Channel means Number of Active High-Priority Channel and
that Number of Low Channel means Number of Active Low-Priority Channel.
11.4.10 Chained Logical Channel Transfers
Chaining multiple logical channels permits transfers consisting of multiple parts to be executed without
repeated software intervention. This results in better performance than the alternative of software setting
up and starting each transfer separately. Each part of a chained transfer can have the data addressed in a
different manner that permits the programming of a variety of complex transfers. For example:
•
Interlaced video data with one logical channel configured to transfer the even lines and another logical
channel configured to transfer the odd lines
•
Protocol headers with a separate DMA4 channel configured to transfer each field in the header
Channels can be chained through each channel
register. When the transfer for the
first channel completes, the next channel in the chain is enabled. The number of channels in the chain
that are configured for hardware-synchronized transfers is flexible (although typically it might be all, none,
or just the first one). The DMA request line number should be set to 0 to specify that any or all of the
channels in a chain are software-triggered or nonsynchronized.
The last channel in a chain can be chained to the first channel to create a continuously looping chain. The
continuously looping transfer can be stopped on the fly at a specific channel by disabling the
[15] ENABLE_LNK bit. The looping transfer stops after the specified channel transfer
is complete.
NOTE:
DMA Request Line
A DMA request line must not be shared between concurrently enabled DMA channels.
However, a DMA request line can be shared between several chained logical channels.
For more information on the programming model, see
, SDMA Basic Programming Model.
11.4.11 Reprogramming an Active Channel
A currently active logical DMA channel can be disabled through the
[7] ENABLE bit. When
any ongoing transaction is complete and the read-active and write-active bits in the
register
(
[9] RD_ACTIVE and
[10] WR_ACTIVE) are reset, the channel can be
reprogrammed for a new transfer.
11.4.12 Interrupt Generation
The SDMA module has four interrupt request output lines, SDMA_IRQ_0 to SDMA_IRQ_3. One or more
logical channels can be programmed to generate an interrupt request on any of these lines when any one
of the maskable DMA events listed in
occurs.
2357
SWPU177N – December 2009 – Revised November 2010
SDMA
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