Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1870 / 3738

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Display Subsystem Register Manual
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Bits Field Name Description Type Reset
31: 9 Reserved Write 0s for future compatibility RW 0x0000000
Read returns 0
8 SMART_DMA_REQ Smart DMA request RW 0x0
0x0: The dmareq is asserted and de-asserted depending on the
interconnect FIFO space even if MIdlereq is high in smart idle/no-idle
mode and the entire burst gets error responses from the module.
0x1: The dmareq is de-asserted after 2 clk cycles if it has been
asserted for more than or equal to 2 clk cycles and MIdlereq is high
in smart idle or no idle mode. No more burst requests will be given
even if the space is available in the interconnect FIFO.
7 DISABLE_DMA_REQ Disable DMA request RW 0x0
0x0: The dmareq is enabled and the signal is generated based on the
space available and the request coming into the data register.
0x1: The dmareq is disabled and the signal is not generated at all
based on space in the interconnect FIFO. It stays high until the
DISABLE DMAREQ is high even if there is space in the interconnect
FIFO to take requests.
6:5 HIGHTHRESHOLD Defines the interconnect FIFO high threshold used by HW to assert RW 0x0
DMA request. Used only if data written to RFBI_DATA are sent using
system DMA.
0x0: Size of the transfer of 4 words of 32-bit wide
0x1: Size of the transfer of 8 words of 32-bit wide
0x2: Size of the transfer of 16 words of 32-bit wide
4 ITE Internal Trigger RW 0
0: H/W waits for ITE bit to be set if in internal trigger mode for the
configuration in use.
1: User sets the ITE bit to start the transfer, when H/W takes into
account the bit, the H/W resets it.
3:2 CONFIGSELECT Select the CS and configuration RW 0x0
00: No CS selected
01: CS0 selected and configuration #0
10: CS1 selected and configuration #1
11: CS0 and CS1 both selected (only the configuration for CS0 is
used)
1 BYPASSMODE Bypass Mode RW 1
0: The bypass mode not selected
1: The bypass mode is selected
0 ENABLE Enable/Disable flag RW 0
0: Disable the RFBI module
1: Enable the RFBI module
Table 7-251. Register Call Summary for Register RFBI_CONTROL
Display Subsystem Environment
• Parallel Interface in RFBI Mode (MIPI DBI Protocol) : [0] [1]
Display Subsystem Basic Programming Model
• RFBI Control Registers : [2]
• High Threshold : [3] [4] [5]
• Bypass Mode : [6]
• Enable : [7] [8] [9]
• Configuration Selection : [10]
• ITE Bit : [11] [12] [13] [14] [15]
• Number of Pixels to Transfer : [16] [17]
• RFBI Configuration : [18]
• Trigger Mode : [19]
• RFBI Timings : [20]
Display Subsystem Register Manual
• RFBI Register Mapping Summary : [21]
1870Display Subsystem SWPU177N – December 2009 – Revised November 2010
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