Texas Instruments OMAP36 Series, Technical Reference Manual

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Camera ISP Basic Programming Model
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6.5.6.6.2.4 Camera ISP CCDC Faulty-Pixel Correction
Faulty-pixel correction is enabled by setting the CCDC_FPC [15] FPCEN bit to 1. Before activating
faulty-pixel correction, set the number of faulty pixels to be corrected in a frame with the CCDC_FPC [14:0]
FPNUM bit field, set the faulty-pixel LUT in memory, and set the CCDC_FPC_ADDR register to the LUT
address. The address should be aligned to a 64-bit byte boundary; the 6 LSBs are ignored. Reading the
register always shows the 6 LSBs as 0.
If the CCDC module cannot fetch the required faulty-pixel entry in time, an error is set in the
CCDC_FPC [16] FPERR bit. After the bit is set, no more faulty pixels are corrected in the frame. The bit is
automatically cleared on the end of the frame and the feature reenabled for the following frame.
6.5.6.6.2.5 Camera ISP CCDC Data Formatter
The data formatter transforms movie mode readout patterns into Bayer readout patterns. It is enabled by
setting
CCDC_FMTCFG [0] FMTEN to 1.
The CCDC_FMT_HORZ and CCDC_FMT_VERT registers set a clip window at the input of the data
reformatter.
The data formatter converts a single line of movie mode sensor into multiple Bayer lines; it is capable of
transforming 1 input line into 1, 2, 3, or 4 output lines. The number of lines generated from one input line
is set by the
CCDC_FMTCFG [3:2] LNUM bit field. The following limitations apply:
• The maximum number of pixels that can be supported in an output line if the input line is transformed
into 1 output line is 4x1376 (1376 is the limit of the line memory).
• The maximum number of pixels that can be supported in an output line if the input line is transformed
into 2 output lines is 2x1376.
• The maximum number of pixels that can be supported in an output line if the input line is transformed
into 3 output lines is 1376.
• The maximum number of pixels that can be supported in an output line if the input line is transformed
into 4 output lines is 1376.
The data reformatter gets its flexibility from up to 8 different addresses and a program that can contain up
to 16 entries each for the odd and even lines. The program length for even fields is set with the
CCDC_FMTCFG [11:8] PLEN_EVEN bit field. The program length for odd fields is set with the
CCDC_FMTCFG [7:4] PLEN_ODD bit fields. Each entry refers to one of the 8 addresses and supports
autoincrement and autodecrement.
• The 8 addresses are controlled by the CCDC_FMT_ADDRx registers (x = 0 to 7).
• The 16 program entries for even lines are controlled by the CCDC_PRGEVEN0 and
CCDC_PRGEVEN1 registers. The 16 program entries for odd lines are controlled by the
CCDC_PRGODD0 and CCDC_PRGODD1 registers.
Modulo addressing is used to access the program entries. Even input lines use the even program and odd
input lines use the odd program. Each new pixel in a line uses one program entry.
The CCDC_VP_OUT register sets the frame size at the output of the video port.
Example 6-2. Conventional readout pattern: 1 input line = 1 output line
The following input-to-output mapping (see Table 6-63 ) corresponds to a conventional readout pattern.
One input line corresponds to 1 output line; the output can be as large as 4x1376 pixels.
Table 6-63. Camera ISP CCDC Conventional Readout Pattern 1 to 1
Input Pixels order in input line
Line [i] 0 1 2 3 [...] 5500 5501 5502 5503
Output Pixels order in output line
Line [i] 0 1 2 3 [...] 5500 5501 5502 5503
1274Camera Image Signal Processor SWPU177N – December 2009 – Revised November 2010
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