Texas Instruments OMAP36 Series, Technical Reference Manual

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Camera ISP Register Manual
Bits Field Name Description Type Reset
23:13 RESERVED Write 0s for future compatibility. RW 0x000
Reads returns 0.
12:0 INIT Initial address value RW 0x0000
If CCDC_FMTCFG .LNUM = 0 (1 line), the max value of
the address must not exceed (4x1376 - 1) including the
updates on it during processing.
If
CCDC_FMTCFG .LNUM = 1 (2 lines), the max value of
the address must not exceed (3x1376 - 1) including the
updates on it during processing.
If
CCDC_FMTCFG .LNUM = 2 (3 lines), the max value of
the address must not exceed (2x1376 - 1) including the
updates on it during processing.
If
CCDC_FMTCFG .LNUM = 3 (4 lines), the max value of
the address must not exceed (1x1376 - 1) including the
updates on it during processing.
The address must always be a positive number during
the updates.
Table 6-262. Register Call Summary for Register CCDC_FMT_ADDR_i
Camera ISP Basic Programming Model
• Camera ISP CCDC Image-Signal Processing : [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17]
Camera ISP Register Manual
• Camera ISP CCDC Register Summary : [18]
Table 6-263. CCDC_PRGEVEN0
Address Offset 0x0000 0084
Physical Address 0x480B C684 Instance ISP_CCDC
Description PROGRAM ENTRIES 0-7 FOR EVEN LINES REGISTER Each bit field in this register is programmed in
the same way. The following definition applies, where n ranges from 0 to 8. Bits [4*n+3:4*n+1] 000:
ADDR0 001: ADDR1 010: ADDR2 011: ADDR3 100: ADDR4 101: ADDR5 110: ADDR6 111: ADDR7 Bit
[4*n]: 0: Auto increment 1: Auto decrement
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EVEN7 EVEN6 EVEN5 EVEN4 EVEN3 EVEN2 EVEN1 EVEN0
Bits Field Name Description Type Reset
31:28 EVEN7 Address update. See register description. RW 0x0
27:24 EVEN6 Address update. See register description. RW 0x0
23:20 EVEN5 Address update. See register description. RW 0x0
19:16 EVEN4 Address update. See register description. RW 0x0
15:12 EVEN3 Address update. See register description. RW 0x0
11:8 EVEN2 Address update. See register description. RW 0x0
7:4 EVEN1 Address update. See register description. RW 0x0
3:0 EVEN0 Address update. See register description. RW 0x0
Table 6-264. Register Call Summary for Register CCDC_PRGEVEN0
Camera ISP Functional Description
• Camera ISP CCDC Functional Operations : [0]
Camera ISP Basic Programming Model
• Camera ISP CCDC Register Setup : [1]
• Camera ISP CCDC Image-Signal Processing : [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
Camera ISP Register Manual
• Camera ISP CCDC Register Summary : [12]
1397 SWPU177N – December 2009 – Revised November 2010 Camera Image Signal Processor
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