Texas Instruments MSP430x1xx, User Manual

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Timer_B Introduction
12-2 Timer_B
12.1 Timer_B Introduction
Timer_B is a 16-bit timer/counter with three or seven capture/compare
registers. Timer_B can support multiple capture/compares, PWM outputs, and
interval timing. Timer_B also has extensive interrupt capabilities. Interrupts
may be generated from the counter on overflow conditions and from each of
the capture/compare registers.
Timer_B features include :
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Asynchronous 16-bit timer/counter with four operating modes and four
selectable lengths
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Selectable and configurable clock source
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Three or seven configurable capture/compare registers
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Configurable outputs with PWM capability
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Double-buffered compare latches with synchronized loading
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Interrupt vector register for fast decoding of all Timer_B interrupts
The block diagram of Timer_B is shown in Figure 12−1.
Note: Use of the Word Count
Count is used throughout this chapter. It means the counter must be in the
process of counting for the action to take place. If a particular value is directly
written to the counter, then an associated action does not take place.
12.1.1 Similarities and Differences From Timer_A
Timer_B is identical to Timer_A with the following exceptions:
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The length of Timer_B is programmable to be 8, 10, 12, or 16 bits.
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Timer_B TBCCRx registers are double-buffered and can be grouped.
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All Timer_B outputs can be put into a high-impedance state.
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The SCCI bit function is not implemented in Timer_B.