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Flash Memory Operation

5-7

Flash Memory Controller

Initiating an Erase from RAM

Any erase cycle may be initiated from RAM. In this case, the CPU is not held
and can continue to execute code from RAM. The BUSY bit must be polled to
determine the end of the erase cycle before the CPU can access any flash
address again. If a flash access occurs while BUSY=1, it is an access violation,
ACCVIFG will be set, and the erase results will be unpredictable.

The flow to initiate an erase from flash from RAM is shown in Figure 5−6.

Figure 5−6. Erase Cycle from Within RAM

yes

BUSY = 1

yes

BUSY = 1

Disable all interrupts and watchdog

Setup flash controller and

erase mode

Dummy write

Set LOCK = 1, re-enable

interrupts and watchdog

; Segment Erase from RAM. 514 kHz < SMCLK < 952 kHz

; Assumes ACCVIE = NMIIE = OFIE = 0.

MOV

#WDTPW+WDTHOLD,&WDTCTL

; Disable WDT

DINT

; Disable interrupts

L1 BIT

#BUSY,&FCTL3

; Test BUSY

JNZ

L1

; Loop while busy

MOV

#FWKEY+FN0,&FCTL2 ; SMCLK/2

MOV

#FWKEY,&FCTL3

; Clear LOCK

MOV

#FWKEY+ERASE,&FCTL1

; Enable erase

CLR

&0FC10h

; Dummy write, erase S1

L2 BIT

#BUSY,&FCTL3

; Test BUSY

JNZ

L2

; Loop while busy

MOV

#FWKEY+LOCK,&FCTL3

; Done, set LOCK

...

; Re-enable WDT?

EINT

; Enable interrupts

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Summary of Contents for MSP430x1xx

Page 1: ... 2005 Mixed Signal Products User s Guide SLAU049E ...

Page 2: ...tute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is...

Page 3: ...he device specific datasheet for these details Related Documentation From Texas Instruments For related documentation see the web site http www ti com msp430 FCC Warning This equipment is intended for use in a laboratory test environment only It gen erates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J o...

Page 4: ...gnificant Bit LSD Least Significant Digit LPM Low Power Mode See System Resets Interrupts and Operating Modes MAB Memory Address Bus MCLK Master Clock See Basic Clock Module MDB Memory Data Bus MSB Most Significant Bit MSD Most Significant Digit NMI Non Maskable Interrupt See System Resets Interrupts and Operating Modes PC Program Counter See RISC 16 Bit CPU POR Power On Reset See System Resets In...

Page 5: ...ondition Register Bit Accessibility and Initial Condition Key Bit Accessibility rw Read write r Read only r0 Read as 0 r1 Read as 1 w Write only w0 Write as 0 w1 Write as 1 w No register bit implemented writing a 1 results in a pulse The register bit is always read as 0 h0 Cleared by hardware h1 Set by hardware 0 1 Condition after PUC 0 1 Condition after POR ...

Page 6: ...vi ...

Page 7: ...errupts and Operating Modes 2 1 2 1 System Reset and Initialization 2 2 2 1 1 Power On Reset POR 2 3 2 1 2 Brownout Reset BOR 2 4 2 1 3 Device Initial Conditions After System Reset 2 5 2 2 Interrupts 2 6 2 2 1 Non Maskable Interrupts NMI 2 7 2 2 2 Maskable Interrupts 2 10 2 2 3 Interrupt Processing 2 11 2 2 4 Interrupt Vectors 2 13 2 3 Operating Modes 2 14 2 3 1 Entering and Exiting Low Power Mode...

Page 8: ...Module 4 1 4 1 Basic Clock Module Introduction 4 2 4 2 Basic Clock Module Operation 4 4 4 2 1 Basic Clock Module Features for Low Power Applications 4 4 4 2 2 LFXT1 Oscillator 4 5 4 2 3 XT2 Oscillator 4 6 4 2 4 Digitally Controlled Oscillator DCO 4 6 4 2 5 DCO Modulator 4 9 4 2 6 Basic Clock Module Fail Safe Operation 4 10 4 2 7 Synchronization of Clock Signals 4 13 4 3 Basic Clock Module Register...

Page 9: ...peration 8 4 8 2 1 DMA Addressing Modes 8 4 8 2 2 DMA Transfer Modes 8 5 8 2 3 Initiating DMA Transfers 8 12 8 2 4 Stopping DMA Transfers 8 14 8 2 5 DMA Channel Priorities 8 14 8 2 6 DMA Transfer Cycle Time 8 15 8 2 7 Using DMA with System Interrupts 8 16 8 2 8 DMA Controller Interrupts 8 16 8 2 9 Using the I2C Module with the DMA Controller 8 17 8 2 10 Using ADC12 with the DMA Controller 8 17 8 2...

Page 10: ...upts 11 17 11 3 Timer_A Registers 11 19 12 Timer_B 12 1 12 1 Timer_B Introduction 12 2 12 1 1 Similarities and Differences From Timer_A 12 2 12 2 Timer_B Operation 12 4 12 2 1 16 Bit Timer Counter 12 4 12 2 2 Starting the Timer 12 5 12 2 3 Timer Mode Control 12 5 12 2 4 Capture Compare Blocks 12 11 12 2 5 Output Unit 12 14 12 2 6 Timer_B Interrupts 12 18 12 3 Timer_B Registers 12 20 13 USART Perip...

Page 11: ...17 15 2 8 I2C Interrupts 15 18 15 3 I2C Module Registers 15 20 16 Comparator_A 16 1 16 1 Comparator_A Introduction 16 2 16 2 Comparator_A Operation 16 4 16 2 1 Comparator 16 4 16 2 2 Input Analog Switches 16 4 16 2 3 Output Filter 16 5 16 2 4 Voltage Reference Generator 16 5 16 2 5 Comparator_A Port Disable Register CAPD 16 6 16 2 6 Comparator_A Interrupts 16 6 16 2 7 Comparator_A Used to Measure ...

Page 12: ...r 18 15 18 2 8 Using the Integrated Temperature Sensor 18 21 18 2 9 ADC10 Grounding and Noise Considerations 18 22 18 2 10 ADC10 Interrupts 18 23 18 3 ADC10 Registers 18 24 19 DAC12 19 1 19 1 DAC12 Introduction 19 2 19 2 DAC12 Operation 19 4 19 2 1 DAC12 Core 19 4 19 2 2 DAC12 Reference 19 5 19 2 3 Updating the DAC12 Voltage Output 19 5 19 2 4 DAC12_xDAT Data Format 19 6 19 2 5 DAC12 Output Amplif...

Page 13: ...1 1 Introduction This chapter describes the architecture of the MSP430 Topic Page 1 1 Architecture 1 2 1 2 Flexible Clock System 1 2 1 3 Embedded Emulation 1 3 1 4 Address Space 1 4 Chapter 1 ...

Page 14: ...ze J Large register file eliminates working file bottleneck J Compact core design reduces power consumption and cost J Optimized for modern high level programming J Only 27 core instructions and seven addressing modes J Extensive vectored interrupt capability In system programmable Flash permits flexible code changes field upgrades and data logging 1 2 Flexible Clock System The clock system is des...

Page 15: ...TAG 1 3 Embedded Emulation Dedicated embedded emulation logic resides on the device itself and is accessed via JTAG using no additional system resources The benefits of embedded emulation include Unobtrusive development and debug with full speed execution breakpoints and single steps in an application are supported Development is in system subject to the same characteristics as the final applicati...

Page 16: ... Function Registers 0FFFFh 0FFDFh 0200h 01FFh 0100h 0FFh 010h 0Fh 0h Access Word Byte Word Byte Word Byte Byte Word Byte 1 4 1 Flash ROM The start address of Flash ROM depends on the amount of Flash ROM present and varies by device The end address for Flash ROM is 0FFFFh Flash can be used for both code and data Word or byte tables can be stored and used in Flash ROM without the need to copy the ta...

Page 17: ...cial Function Registers SFRs Some peripheral functions are configured in the SFRs The SFRs are located in the lower 16 bytes of the address space and are organized by byte SFRs must be accessed using byte instructions only See the device specific data sheets for applicable SFR bits 1 4 5 Memory Organization Bytes are located at even or odd addresses Words are only located at even addresses as show...

Page 18: ...1 6 Introduction ...

Page 19: ...ter describes the MSP430x1xx system resets interrupts and operating modes Topic Page 2 1 System Reset and Initialization 2 2 2 2 Interrupts 2 6 2 3 Operating Modes 2 14 2 4 Principles for Low Power Applications 2 17 2 5 Connection of Unused Pins 2 17 Chapter 2 ...

Page 20: ... WDTQn WDTIFG EQU MCLK POR PUC 0 V S from flash module KEYV POR Detect VCC 0 V POR Delay VCC 0 V SVS_POR 0 V VCC 0 V Brownout Reset From watchdog timer peripheral module Devices with BOR only Devices without BOR only Devices with SVS only 50us A POR is a device reset A POR is only generated by the following three events Powering up the device A low signal on the RST NMI pin when configured in the ...

Page 21: ..._DELAY provides active time on the POR signal to allow the MSP430 to initialize If power to the MSP430 is cycled the supply voltage VCC must fall below Vmin to ensure that another POR signal occurs when VCC is powered up again If VCC does not fall below Vmin during a cycle or a glitch a POR is not generated and power up conditions do not set correctly See device specific datasheet for parameters F...

Page 22: ...s are shown in Figure 2 3 The POR signal becomes active when VCC crosses the VCC start level It remains active until VCC crosses the V B_IT threshold and the delay t BOR elapses The delay t BOR is adaptive being longer for a slow ramping VCC The hysteresis Vhys B_ IT ensures that the supply voltage must drop below V B_IT to generate another POR signal from the brownout reset circuitry Figure 2 3 B...

Page 23: ...SR is reset The watchdog timer powers up active in watchdog mode Program counter PC is loaded with address contained at reset vector location 0FFFEh CPU execution begins at that address Software Initialization After a system reset user software must initialize the MSP430 for the application requirements The following must occur Initialize the SP typically to the top of RAM Initialize the watchdog ...

Page 24: ...e CPU NMIRS the higher the priority Interrupt priorities determine what interrupt is taken when more than one interrupt is pending simultaneously There are three types of interrupts System reset Non maskable NMI Maskable Figure 2 4 Interrupt Priority Bus Grant Module 1 Module 2 WDT Timer Module m Module n 1 2 1 2 1 2 1 2 1 NMIRS GIE CPU OSCfault Reset NMI PUC Circuit PUC WDT Security Key Priority ...

Page 25: ...ction of the RST NMI pins is selected in the watchdog control register WDTCTL If the RST NMI pin is set to the reset function the CPU is held in the reset state as long as the RST NMI pin is held low After the input changes to a high state the CPU starts program execution at the word address stored in the reset vector 0FFFEh If the RST NMI pin is configured by user software to the NMI function a s...

Page 26: ...et Generator VCC POR PUC WDTQn EQU PUC POR PUC POR NMIRS Clear S WDTIFG IRQ WDTIE Clear IE1 0 PUC POR IRQA WDTTMSEL Counter IFG1 0 WDTNMI WDTTMSEL WDTNMIES Watchdog Timer Module Clear S IFG1 4 PUC Clear IE1 4 PUC NMIIFG NMIIE S IFG1 1 Clear IE1 1 PUC OFIFG OFIE OSCFault NMI_IRQA IRQA Interrupt Request Accepted RST NMI S FCTL1 1 Clear IE1 5 ACCVIFG ACCVIE PUC ACCV WDT ...

Page 27: ...if the NMI was caused by a flash access violation Oscillator Fault The oscillator fault signal warns of a possible error condition with the crystal oscillator The oscillator fault can be enabled to generate an NMI interrupt by setting the OFIE bit The OFIFG flag can then be tested by NMI the interrupt service routine to determine if the NMI was caused by an oscillator fault A PUC signal can trigge...

Page 28: ... External NMI Handler Optional Set NMIIE OFIE ACCVIE Within One Instruction RETI End of NMI Interrupt Handler Example 1 Example 2 BIS NMIIE OFIE ACCVIE IE1 BIS Mask IE1 Mask enables only interrupt sources Note Enabling NMI Interrupts with ACCVIE NMIIE and OFIE The ACCVIE NMIIE and OFIE enable bits should not be set inside of an NMI interrupt service routine unless they are set by the last instruct...

Page 29: ... 7 The interrupt logic executes the following 1 Any currently executing instruction is completed 2 The PC which points to the next instruction is pushed onto the stack 3 The SR is pushed onto the stack 4 The interrupt with the highest priority is selected if multiple interrupts occurred during the last instruction and are pending for service 5 The interrupt request flag resets automatically on sin...

Page 30: ...ious settings of GIE CPUOFF etc are now in effect regardless of the settings used during the interrupt service routine 2 The PC pops from the stack and begins execution at the point where it was interrupted Figure 2 8 Return From Interrupt Item1 Item2 SP TOS Item1 Item2 SP TOS PC SR Before After PC SR Return From Interrupt Interrupt Nesting Interrupt nesting is enabled if the GIE bit is set inside...

Page 31: ...et 0FFFEh 15 highest NMI oscillator fault flash memory access violation NMIIFG OFIFG ACCVIFG non maskable non maskable non maskable 0FFFCh 14 device specific 0FFFAh 13 device specific 0FFF8h 12 device specific 0FFF6h 11 Watchdog timer WDTIFG maskable 0FFF4h 10 device specific 0FFF2h 9 device specific 0FFF0h 8 device specific 0FFEEh 7 device specific 0FFECh 6 device specific 0FFEAh 5 device specifi...

Page 32: ...status register The advantage of including the CPUOFF OSCOFF SCG0 and SCG1 mode control bits in the status register is that the present operating mode is saved onto the stack during an interrupt service routine Program flow returns to the previous operating mode if the saved SR value is not altered during the interrupt service routine Program flow can be returned to a different operating mode by m...

Page 33: ...WDT Active Security Key Violation WDT Time Expired Overflow WDTIFG 1 WDTIFG 1 RST NMI Reset Active VCC On WDTIFG 0 LPM1 CPU Off MCLK Off SMCLK On ACLK On DC Generator Off if DCO not used in active mode CPUOFF 1 SCG0 1 SCG1 1 SCG1 SCG0 OSCOFF CPUOFF Mode CPU and Clocks Status 0 0 0 0 Active CPU is active all enabled clocks are active 0 0 0 1 LPM0 CPU MCLK are disabled SMCLK ACLK are active 0 1 0 1 ...

Page 34: ...rvice Routine BIC CPUOFF 0 SP Exit LPM0 on RETI RETI Enter LPM3 Example BIS GIE CPUOFF SCG1 SCG0 SR Enter LPM3 Program stops here Exit LPM3 Interrupt Service Routine BIC CPUOFF SCG1 SCG0 0 SP Exit LPM3 on RETI RETI Extended Time in Low Power Modes The negative temperature coefficient of the DCO should be considered when the DCO is disabled for extended low power mode periods If the temperature cha...

Page 35: ...er_A and Timer_B can automatically generate PWM and capture external timing with no CPU resources Calculated branching and fast table look ups should be used in place of flag polling and long software calculations Avoid frequent subroutine and function calls due to overhead For longer software routines single cycle CPU registers should be used 2 5 Connection of Unused Pins The correct termination ...

Page 36: ...2 18 System Resets Interrupts and Operating Modes ...

Page 37: ...ISC 16 Bit CPU This chapter describes the MSP430 CPU addressing modes and instruction set Topic Page 3 1 CPU Introduction 3 2 3 2 CPU Registers 3 4 3 3 Addressing Modes 3 9 3 4 Instruction Set 3 17 Chapter 3 ...

Page 38: ...y instruction usable with every addressing mode Full register access including program counter status registers and stack pointer Single cycle register operations Large 16 bit register file reduces fetches to memory 16 bit address bus allows direct access and branching throughout entire memory range 16 bit data bus allows direct manipulation of word wide arguments Constant generator provides six m...

Page 39: ... N 16 bit ALU dst src R8 General Purpose R9 General Purpose R10 General Purpose R11 General Purpose R12 General Purpose R13 General Purpose R14 General Purpose R15 General Purpose R4 General Purpose R5 General Purpose R6 General Purpose R7 General Purpose R3 CG2 Constant Generator R2 SR CG1 Status R1 SP Stack Pointer R0 PC Program Counter 0 0 16 MCLK ...

Page 40: ...an even number of bytes two four or six and the PC is incremented accordingly Instruction accesses in the 64 KB address space are performed on word boundaries and the PC is aligned to even addresses Figure 3 2 shows the program counter Figure 3 2 Program Counter 0 15 0 Program Counter Bits 15 to 1 1 The PC can be addressed with all instructions and addressing modes A few examples MOV LABEL PC Bran...

Page 41: ...0 15 0 Stack Pointer Bits 15 to 1 1 MOV 2 SP R6 Item I2 R6 MOV R7 0 SP Overwrite TOS with R7 PUSH 0123h Put 0123h onto TOS POP R8 R8 0123h Figure 3 4 Stack Usage I3 I1 I2 I3 0xxxh 0xxxh 2 0xxxh 4 0xxxh 6 0xxxh 8 I1 I2 SP 0123h SP I1 I2 I3 SP PUSH 0123h POP R8 Address 0123h The special cases of using the SP as an argument to the PUSH and POP instructions are described and shown in Figure 3 5 Figure...

Page 42: ...Positive otherwise reset SCG1 System clock generator 1 This bit when set turns off the SMCLK SCG0 System clock generator 0 This bit when set turns off the DCO dc generator if DCOCLK is not used for MCLK or SMCLK OSCOFF Oscillator Off This bit when set turns off the LFXT1 crystal oscillator when LFXT1CLK is not use for MCLK or SMCLK CPUOFF CPU off This bit when set turns off the CPU GIE General int...

Page 43: ...enerator advantages are No special instructions required No additional code word for the six constants No code memory access required to retrieve the constant The assembler uses the constant generator automatically if one of the six constants is used as an immediate source operand Registers R2 and R3 used in the constant mode cannot be addressed explicitly they act as source only registers Constan...

Page 44: ...Register Operations Unused High Byte Low Byte Byte Register Byte Operation 0h High Byte Low Byte Byte Byte Register Operation Register Memory Register Memory Example Register Byte Operation Example Byte Register Operation R5 0A28Fh R5 01202h R6 0203h R6 0223h Mem 0203h 012h Mem 0223h 05Fh ADD B R5 0 R6 ADD B R6 R5 08Fh 05Fh 012h 002h 0A1h 00061h Mem 0203h 0A1h R5 00061h C 0 Z 0 N 1 C 0 Z 0 N 0 Low...

Page 45: ...llowing the instruction contains the absolute address X is stored in the next word Indexed mode X SR is used 10 Indirect register mode Rn Rn is used as a pointer to the operand 11 Indirect autoincrement Rn Rn is used as a pointer to the operand Rn is incremented afterwards by 1 for B instructions and by 2 for W instructions 11 Immediate mode N The word following the instruction contains the immedi...

Page 46: ...ove the content of R10 to R11 R10 is not affected Comment Valid for source and destination Example MOV R10 R11 0A023h R10 R11 Before After PC 0FA15h PCold 0A023h R10 R11 PC PCold 2 0A023h Note Data in Registers The data in the register can be accessed using word or byte instructions If byte instructions are used the high byte is always 0 in the result The status bits are handled according to the r...

Page 47: ...cted In indexed mode the program counter is incremented automatically so that program execution continues with the next instruction Comment Valid for source and destination Example MOV 2 R5 6 R6 00006h Address Space 00002h 04596h PC 0FF16h 0FF14h 0FF12h 0xxxxh 05555h 01094h 01092h 01090h 0xxxxh 0xxxxh 01234h 01084h 01082h 01080h 0xxxxh 01080h 0108Ch R5 R6 0108Ch 0006h 01092h 01080h 0002h 01082h Re...

Page 48: ...e assembler computes and inserts offsets X and Y automatically With symbolic mode the program counter PC is incremented automatically so that program execution continues with the next instruction Comment Valid for source and destination Example MOV EDE TONI Source address EDE 0F016h Dest address TONI 01114h 011FEh Address Space 0F102h 04090h PC 0FF16h 0FF14h 0FF12h 0xxxxh 0A123h 0F018h 0F016h 0F01...

Page 49: ...tion continues with the next instruction Comment Valid for source and destination Example MOV EDE TONI Source address EDE 0F016h dest address TONI 01114h 01114h Address Space 0F016h 04292h PC 0FF16h 0FF14h 0FF12h 0xxxxh 0A123h 0F018h 0F016h 0F014h 0xxxxh 0xxxxh 01234h 01116h 01114h 01112h 0xxxxh Register Before 01114h Address Space 0F016h 04292h PC 0FF16h 0FF14h 0FF12h 0xxxxh 0A123h 0F018h 0F016h ...

Page 50: ...address contents of R11 The registers are not modified Comment Valid only for source operand The substitute for destination operand is 0 Rd Example MOV B R10 0 R11 0000h Address Space 04AEBh PC 0FF16h 0FF14h 0FF12h 0xxxxh 05BC1h 0xxxxh 0xxh 012h 0xxh 0FA33h 002A7h R10 R11 Register Before 0000h Address Space 04AEBh PC 0FF16h 0FF14h 0FF12h 0xxxxh 05BC1h 0FA34h 0FA32h 0FA30h 0xxxxh 0xxh 05Bh 002A8h 0...

Page 51: ...eful for table processing Comment Valid only for source operand The substitute for destination operand is 0 Rd plus second instruction INCD Rd Example MOV R10 0 R11 00000h Address Space 04ABBh PC 0FF16h 0FF14h 0FF12h 0xxxxh 05BC1h 0FA34h 0FA32h 0FA30h 0xxxxh 0xxxxh 01234h 010AAh 010A8h 010A6h 0xxxxh 0FA32h 010A8h R10 R11 Register Before Address Space 0xxxxh 05BC1h 0FA34h 0FA32h 0FA30h 0xxxxh 0xxxx...

Page 52: ...ich is contained in the word following the instruction to destination address TONI When fetching the source the program counter points to the word following the instruction and moves the contents to the destination Comment Valid only for a source operand Example MOV 45h TONI 01192h Address Space 00045h 040B0h PC 0FF16h 0FF14h 0FF12h 0xxxxh 01234h 0xxxxh 0FF16h 01192h 010A8h Register Before 01192h ...

Page 53: ...d to access word data or word peripherals If no extension is used the instruction is a word instruction The source and destination of an instruction are defined by the following fields src The source operand defined by As and S reg dst The destination operand defined by Ad and D reg As The addressing bits responsible for the addressing mode used for the source src S reg The working register used f...

Page 54: ...C MOV B src dst src dst ADD B src dst src dst dst ADDC B src dst src dst C dst SUB B src dst dst not src 1 dst SUBC B src dst dst not src C dst CMP B src dst dst src DADD B src dst src dst C dst decimally BIT B src dst src and dst 0 BIC B src dst not src and dst dst BIS B src dst src or dst dst XOR B src dst src xor dst dst AND B src dst src and dst dst 0 The status bit is affected The status bit ...

Page 55: ...Reg D Reg Operation Status Bits D Reg V N Z C RRC B dst C MSB LSB C RRA B dst MSB MSB LSB C 0 PUSH B src SP 2 SP src SP SWPB dst Swap bytes CALL dst SP 2 SP PC 2 SP dst PC RETI TOS SR SP 2 SP TOS PC SP 2 SP SXT dst Bit 7 Bit 8 Bit 15 0 The status bit is affected The status bit is not affected 0 The status bit is cleared 1 The status bit is set All addressing modes are possible for the CALL instruc...

Page 56: ...ro bit is reset JC Label Jump to label if carry bit is set JNC Label Jump to label if carry bit is reset JN Label Jump to label if negative bit is set JGE Label Jump to label if N XOR V 0 JL Label Jump to label if N XOR V 1 JMP Label Jump to label unconditionally Conditional jumps support program branching relative to the PC and do not affect the status bits The possible jump range is from 511 to ...

Page 57: ...tive Z Set if result is zero reset otherwise C Set if dst was incremented from 0FFFFh to 0000 reset otherwise Set if dst was incremented from 0FFh to 00 reset otherwise V Set if an arithmetic overflow occurs otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 16 bit counter pointed to by R13 is added to a 32 bit counter pointed to by R12 ADD R13 0 R12 Add LSDs ADC 2 R12 Ad...

Page 58: ...tatus Bits N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the result cleared if not V Set if an arithmetic overflow occurs otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example R5 is increased by 10 The jump to TONI is performed on a carry ADD 10 R5 JC TONI Carry occurred No carry Example R5 is increased by 10...

Page 59: ...herwise C Set if there is a carry from the MSB of the result reset otherwise V Set if an arithmetic overflow occurs otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 32 bit counter pointed to by R13 is added to a 32 bit counter eleven words 20 2 2 2 above the pointer in R13 ADD R13 20 R13 ADD LSDs with no carry in ADDC R13 20 R13 ADD MSDs with carry resulting from the LS...

Page 60: ...ise C Set if result is not zero reset otherwise NOT Zero V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The bits set in R5 are used as a mask 0AA55h for the word addressed by TOM If the result is zero a branch is taken to label TONI MOV 0AA55h R5 Load mask into register R5 AND R5 TOM mask word addressed by TOM with R5 JZ TONI Result is not zero or AND 0AA55h TOM JZ TONI Example T...

Page 61: ...perand and the destination operand are logically ANDed The result is placed into the destination The source operand is not affected Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The six MSBs of the RAM word LEO are cleared BIC 0FC00h LEO Clear 6 MSBs in MEM LEO Example The five MSBs of the RAM byte LEO are cleared BIC B 0F8h LEO Clear 5 MSBs in R...

Page 62: ... the destination operand are logically ORed The result is placed into the destination The source operand is not affected Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The six LSBs of the RAM word TOM are set BIS 003Fh TOM set the six LSBs in RAM location TOM Example The three MSBs of RAM byte TOM are set BIS B 0E0h TOM set the 3 MSBs in RAM locat...

Page 63: ... R8 bit 9 of R8 set JNZ TOM Yes branch to TOM No proceed Example If bit 3 of R8 is set a branch is taken to label TOM BIT B 8 R8 JC TOM Example A serial communication receive bit RCV is tested Because the carry bit is equal to the state of the tested bit while using the BIT instruction to test a single bit the carry bit is used by the subsequent instruction the read information is shifted into reg...

Page 64: ...o the address contained in absolute address EXEC Core instruction MOV X 0 PC Indirect address BR R5 Branch to the address contained in R5 Core instruction MOV R5 PC Indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 Core instruction MOV R5 PC Indirect indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 and increment pointer in R5 afterwards Th...

Page 65: ...ained in EXEC SP 2 SP PC 2 SP X PC PC Indirect address CALL EXEC Call on the address contained in absolute address EXEC SP 2 SP PC 2 SP X 0 PC Indirect address CALL R5 Call on the address contained in R5 SP 2 SP PC 2 SP R5 PC Indirect R5 CALL R5 Call on the address contained in the word pointed to by R5 SP 2 SP PC 2 SP R5 PC Indirect indirect R5 CALL R5 Call on the address contained in the word po...

Page 66: ...st or CLR W dst CLR B dst Operation 0 dst Emulation MOV 0 dst MOV B 0 dst Description The destination operand is cleared Status Bits Status bits are not affected Example RAM word TONI is cleared CLR TONI 0 TONI Example Register R5 is cleared CLR R5 Example RAM byte TONI is cleared CLR B TONI 0 TONI ...

Page 67: ... a word instruction Status Bits N Not affected Z Not affected C Cleared V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 16 bit decimal counter pointed to by R13 is added to a 32 bit counter pointed to by R12 CLRC C 0 defines start DADD R13 0 R12 add 16 bit counter to low word of 32 bit counter DADC 2 R12 add carry to high word of 32 bit counter ...

Page 68: ... result is placed into the destination The clear negative bit instruction is a word instruction Status Bits N Reset to 0 Z Not affected C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The Negative bit in the status register is cleared This avoids special treatment with negative numbers of the subroutine called CLRN CALL SUBR SUBR JN SUBRET If input is negativ...

Page 69: ...nt 02h is inverted 0FFFDh and logically ANDed with the destination operand The result is placed into the destination The clear zero bit instruction is a word instruction Status Bits N Not affected Z Reset to 0 C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The zero bit in the status register is cleared CLRZ ...

Page 70: ... result reset otherwise V Set if an arithmetic overflow occurs otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example R5 and R6 are compared If they are equal the program continues at the label EQUAL CMP R5 R6 R5 R6 JEQ EQUAL YES JUMP Example Two RAM blocks are compared If they are not equal the program branches to the label ERROR MOV NUM R5 number of words to be compared MOV BLO...

Page 71: ...9 to 0000 reset otherwise Set if destination increments from 99 to 00 reset otherwise V Undefined Mode Bits OSCOFF CPUOFF and GIE are not affected Example The four digit decimal number contained in R5 is added to an eight digit deci mal number pointed to by R8 CLRC Reset carry next instruction s start condition is defined DADD R5 0 R8 Add LSDs C DADC 2 R8 Add carry to MSD Example The two digit dec...

Page 72: ...ost The result is not defined for non BCD numbers Status Bits N Set if the MSB is 1 reset otherwise Z Set if result is zero reset otherwise C Set if the result is greater than 9999 Set if the result is greater than 99 V Undefined Mode Bits OSCOFF CPUOFF and GIE are not affected Example The eight digit BCD number contained in R5 and R6 is added decimally to an eight digit BCD number contained in R3...

Page 73: ...rs otherwise reset Set if initial value of destination was 08000h otherwise reset Set if initial value of destination was 080h otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example R10 is decremented by 1 DEC R10 Decrement R10 Move a block of 255 bytes from memory location starting with EDE to memory location starting with TONI Tables should not overlap start of destination addr...

Page 74: ... occurs otherwise reset Set if initial value of destination was 08001 or 08000h otherwise reset Set if initial value of destination was 081 or 080h otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example R10 is decremented by 2 DECD R10 Decrement R10 by two Move a block of 255 words from memory location starting with EDE to memory location starting with TONI Tables should not over...

Page 75: ...ted Example The general interrupt enable GIE bit in the status register is cleared to allow a nondisrupted move of a 32 bit counter This ensures that the counter is not modified during the move by any interrupt DINT All interrupt events using the GIE bit are disabled NOP MOV COUNTHI R5 Copy counter MOV COUNTLO R6 EINT All interrupt events using the GIE bit are enabled Note Disable Interrupt If any...

Page 76: ...orts P1 2 to P1 7 P1IN is the address of the register where all port bits are read P1IFG is the address of the register where all interrupt events are latched PUSH B P1IN BIC B SP P1IFG Reset only accepted flags EINT Preset port 1 interrupt flags stored on stack other interrupts are allowed BIT Mask SP JEQ MaskOK Flags are present identically to mask jump MaskOK BIC Mask SP INCD SP Housekeeping in...

Page 77: ... is negative reset if positive Z Set if dst contained 0FFFFh reset otherwise Set if dst contained 0FFh reset otherwise C Set if dst contained 0FFFFh reset otherwise Set if dst contained 0FFh reset otherwise V Set if dst contained 07FFFh reset otherwise Set if dst contained 07Fh reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example The status byte STATUS of a process is increment...

Page 78: ...herwise C Set if dst contained 0FFFEh or 0FFFFh reset otherwise Set if dst contained 0FEh or 0FFh reset otherwise V Set if dst contained 07FFEh or 07FFFh reset otherwise Set if dst contained 07Eh or 07Fh reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example The item on the top of the stack TOS is removed without using a register PUSH R5 R5 is the result of a calculation which is...

Page 79: ...t otherwise Set if dst contained 0FFh reset otherwise C Set if result is not zero reset otherwise NOT Zero Set if result is not zero reset otherwise NOT Zero V Set if initial destination operand was negative otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example Content of R5 is negated twos complement MOV 00AEh R5 R5 000AEh INV R5 Invert R5 R5 0FF51h INC R5 R5 is now negated R5 ...

Page 80: ...ter If C is reset the next instruction following the jump is executed JC jump if carry higher or same is used for the comparison of unsigned numbers 0 to 65536 Status Bits Status bits are not affected Example The P1IN 1 signal is used to define or control the program flow BIT 01h P1IN State of signal Carry JC PROGA If carry 1 then execute program routine A Carry 0 execute program here Example R5 i...

Page 81: ...s added to the program counter If Z is not set the instruction following the jump is executed Status Bits Status bits are not affected Example Jump to address TONI if R7 contains zero TST R7 Test R7 JZ TONI if zero JUMP Example Jump to address LEO if R6 is equal to the table contents CMP R6 Table R5 Compare content of R6 with content of MEM table address content of R5 JEQ LEO Jump if both data are...

Page 82: ...sted If both N and V are set or reset the 10 bit signed offset contained in the instruction LSBs is added to the program counter If only one is set the instruction following the jump is executed This allows comparison of signed integers Status Bits Status bits are not affected Example When the content of R6 is greater or equal to the memory pointed to by R7 the program continues at label EDE CMP R...

Page 83: ...d If only one is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If both N and V are set or reset the instruction following the jump is executed This allows comparison of signed integers Status Bits Status bits are not affected Example When the content of R6 is less than the memory pointed to by R7 the program continues at label EDE CMP R7 R6 R6 R7 co...

Page 84: ... 2 offset PC Description The 10 bit signed offset contained in the instruction LSBs is added to the program counter Status Bits Status bits are not affected Hint This one word instruction replaces the BRANCH instruction in the range of 511 to 512 words relative to the current program counter ...

Page 85: ...d in the instruction LSBs is added to the program counter If N is reset the next instruction following the jump is executed Status Bits Status bits are not affected Example The result of a computation in R5 is to be subtracted from COUNT If the result is negative COUNT is to be cleared and the program continues execution in another path SUB R5 COUNT COUNT R5 COUNT JN L 1 If negative continue with ...

Page 86: ... C is set the next instruction following the jump is executed JNC jump if no carry lower is used for the comparison of unsigned numbers 0 to 65536 Status Bits Status bits are not affected Example The result in R6 is added in BUFFER If an overflow occurs an error handling routine at address ERROR is used ADD R6 BUFFER BUFFER R6 BUFFER JNC CONT No carry jump to CONT ERROR Error handler start CONT Co...

Page 87: ...he status register zero bit Z is tested If it is reset the 10 bit signed offset contained in the instruction LSBs is added to the program counter If Z is set the next instruction following the jump is executed Status Bits Status bits are not affected Example Jump to address TONI if R7 and R8 have different contents CMP R7 R8 COMPARE R7 WITH R8 JNE TONI if different jump if equal continue ...

Page 88: ... contents of table EDE word data are copied to table TOM The length of the tables must be 020h locations MOV EDE R10 Prepare pointer MOV 020h R9 Prepare counter Loop MOV R10 TOM EDE 2 R10 Use pointer in R10 for both tables DEC R9 Decrement counter JNZ Loop Counter 0 continue copying Copying completed Example The contents of table EDE byte data are copied to table TOM The length of the tables shoul...

Page 89: ...ing Note Emulating No Operation Instruction Other instructions can emulate the NOP function while providing different numbers of instruction cycles and code words Some examples are Examples MOV 0 R3 1 cycle 1 word MOV 0 R4 0 R4 6 cycles 3 words MOV R4 0 R4 5 cycles 2 words BIC 0 EDE R4 4 cycles 2 words JMP 2 2 cycles 1 word BIC 0 R5 1 cycle 1 word However care should be taken when using these exam...

Page 90: ...POP SR Restore status register Example The contents of RAM byte LEO is restored from the stack POP B LEO The low byte of the stack is moved to LEO Example The contents of R7 is restored from the stack POP B R7 The low byte of the stack is moved to R7 the high byte of R7 is 00h Example The contents of the memory pointed to by R7 and the status register are restored from the stack POP B 0 R7 The low...

Page 91: ... pointer TOS Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The contents of the status register and R8 are saved on the stack PUSH SR save status register PUSH R8 save R8 Example The contents of the peripheral TCDAT is saved on the stack PUSH B TCDAT save data from 8 bit peripheral module address TCDAT onto stack Note The System Stack Pointer The ...

Page 92: ...ax RET Operation SP PC SP 2 SP Emulation MOV SP PC Description The return address pushed onto the stack by a CALL instruction is moved to the program counter The program continues at the code address following the subroutine call Status Bits Status bits are not affected ...

Page 93: ...s the consecutive step after the interrupted program flow Restoration is performed by replacing the present PC contents with the TOS memory contents The stack pointer SP is incremented Status Bits N restored from system stack Z restored from system stack C restored from system stack V restored from system stack Mode Bits OSCOFF CPUOFF and GIE are restored from system stack Example Figure 3 13 illu...

Page 94: ...7 0 C Byte Word 0 An overflow occurs if dst 040h and dst 0C0h before the operation is performed the result has changed sign Status Bits N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Loaded from the MSB V Set if an arithmetic overflow occurs the initial value is 04000h dst 0C000h reset otherwise Set if an arithmetic overflow occurs the initial value is 040h...

Page 95: ...e Z Set if result is zero reset otherwise C Loaded from the MSB V Set if an arithmetic overflow occurs the initial value is 04000h dst 0C000h reset otherwise Set if an arithmetic overflow occurs the initial value is 040h dst 0C0h reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example R5 is shifted left one position RLC R5 R5 x 2 C R5 Example The input P1IN 1 information is shifte...

Page 96: ...et if result is zero reset otherwise C Loaded from the LSB V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example R5 is shifted right one position The MSB retains the old value It operates equal to an arithmetic division by 2 RRA R5 R5 2 R5 The value in R5 is multiplied by 0 75 0 5 0 25 PUSH R5 Hold R5 temporarily using stack RRA R5 R5 0 5 R5 ADD SP R5 R5 0 5 R5 1 5 R5 R5 RRA R5 1 5 R5 0...

Page 97: ...stination Operand Carry Right Shift 15 0 7 0 C Byte Word Status Bits N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Loaded from the LSB V Set if initial destination is positive and initial carry is set otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example R5 is shifted right one position The MSB is loaded with 1 SETC Prepare carry for MSB...

Page 98: ...if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Set if an arithmetic overflow occurs reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 16 bit counter pointed to by R13 is subtracted from a 32 bit counter pointed to by R12 SUB R13 0 R12 Subtract LSDs SBC 2 R12 Subtract carry fro...

Page 99: ...cted Mode Bits OSCOFF CPUOFF and GIE are not affected Example Emulation of the decimal subtraction Subtract R5 from R6 decimally Assume that R5 03987h and R6 04137h DSUB ADD 06666h R5 Move content R5 from 0 9 to 6 0Fh R5 03987h 06666h 09FEDh INV R5 Invert this result back to 0 9 R5 NOT R5 06012h SETC Prepare carry 1 DADD R5 R6 Emulate subtraction by addition of 010000h R5 1 R6 R6 R5 1 R6 0150h ...

Page 100: ...16 Bit CPU SETN Set negative bit Syntax SETN Operation 1 N Emulation BIS 4 SR Description The negative bit N is set Status Bits N Set Z Not affected C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected ...

Page 101: ...ISC 16 Bit CPU SETZ Set zero bit Syntax SETZ Operation 1 Z Emulation BIS 2 SR Description The zero bit Z is set Status Bits N Not affected Z Set C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected ...

Page 102: ...and is not affected The previous contents of the destination are lost Status Bits N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Set if an arithmetic overflow occurs otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example See example a...

Page 103: ...Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Set if an arithmetic overflow occurs reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example Two floating point mantissas 24 bits are subtracted LSBs are in R13 and R10 MSBs are in R12 and R...

Page 104: ...tatus Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Figure 3 18 Destination Operand Byte Swap 15 8 7 0 Example MOV 040BFh R7 0100000010111111 R7 SWPB R7 1011111101000000 in R7 Example The value in R5 is multiplied by 256 The result is stored in R5 R4 SWPB R5 MOV R5 R4 Copy the swapped value to R4 BIC 0FF00h R5 Correct the result BIC 00FFh R4 Correct the result ...

Page 105: ...ositive Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise NOT Zero V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Figure 3 19 Destination Operand Sign Extension 15 8 7 0 Example R7 is loaded with the P1IN value The operation of the sign extend instruction expands bit 8 to bit 15 with the value of bit 7 R7 is then added to R6 MOV B P1IN R7 P1IN 080h 1000 ...

Page 106: ...rwise C Set V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example R7 is tested If it is negative continue at R7NEG if it is positive but not zero continue at R7POS TST R7 Test R7 JN R7NEG R7 is negative JZ R7ZERO R7 is zero R7POS R7 is positive but not zero R7NEG R7 is negative R7ZERO R7 is zero Example The low byte of R7 is tested If it is negative continue at R7NEG if it is positive b...

Page 107: ...Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise NOT Zero V Set if both operands are negative Mode Bits OSCOFF CPUOFF and GIE are not affected Example The bits set in R6 toggle the bits in the RAM word TONI XOR R6 TONI Toggle bits of word TONI on the bits set in R6 Example The bits set in R6 toggle the bits in the RAM byte TONI XOR B R6 TONI Toggle bits of byte T...

Page 108: ...les and Lengths Table 3 15 lists the length and CPU cycles for all addressing modes of format II instructions Table 3 15 Format II Instruction Cycles and Lengths No of Cycles Addressing Mode RRA RRC SWPB SXT PUSH CALL Length of Instruction Example Rn 1 3 4 1 SWPB R5 Rn 3 4 4 1 RRC R9 Rn 3 5 5 1 SWPB R10 N See note 4 5 2 CALL 0F000h X Rn 4 5 5 2 CALL 2 R7 EDE 4 5 5 2 PUSH EDE EDE 4 5 5 2 SXT EDE No...

Page 109: ...MOV R5 EDE Rn Rm 2 1 AND R4 R5 Rn PC 2 1 BR R8 x Rm 5 2 XOR R5 8 R6 EDE 5 2 MOV R5 EDE EDE 5 2 XOR R5 EDE Rn Rm 2 1 ADD R5 R6 Rn PC 3 1 BR R9 x Rm 5 2 XOR R5 8 R6 EDE 5 2 MOV R9 EDE EDE 5 2 MOV R9 EDE N Rm 2 2 MOV 20 R9 N PC 3 2 BR 2AEh x Rm 5 3 MOV 0300h 0 SP EDE 5 3 ADD 33 EDE EDE 5 3 ADD 33 EDE x Rn Rm 3 2 MOV 2 R5 R7 x Rn PC 3 2 BR 2 R6 TONI 6 3 MOV 4 R7 TONI x Rm 6 3 ADD 4 R4 6 R9 TONI 6 3 MO...

Page 110: ...x 4xxx 8xxx Cxxx 1xxx 14xx 18xx 1Cxx 20xx 24xx 28xx 2Cxx 30xx 34xx 38xx 3Cxx 4xxx 5xxx 6xxx 7xxx 8xxx 9xxx Axxx Bxxx Cxxx Dxxx Exxx Fxxx RRC RRC B SWPB RRA RRA B SXT PUSH PUSH B CALL RETI 000 040 080 0C0 100 140 180 1C0 200 240 280 2C0 300 340 380 3C0 JNE JNZ JEQ JZ JNC JC JN JGE JL JMP MOV MOV B ADD ADD B ADDC ADDC B SUBC SUBC B SUB SUB B CMP CMP B DADD DADD B BIT BIT B BIC BIC B BIS BIS B XOR XO...

Page 111: ...destination dst 1 dst INCD B dst Double increment destination dst 2 dst INV B dst Invert destination not dst dst JC JHS label Jump if C set Jump if higher or same JEQ JZ label Jump if equal Jump if Z set JGE label Jump if greater or equal JL label Jump if less JMP label Jump PC 2 x offset PC JN label Jump if N set JNC JLO label Jump if C not set Jump if lower JNE JNZ label Jump if not equal Jump i...

Page 112: ...3 76 ...

Page 113: ...0x1xx devices This chapter describes the operation of the basic clock module The basic clock module is implemented in all MSP430x1xx devices Topic Page 4 1 Basic Clock Module Introduction 4 2 4 2 Basic Clock Module Operation 4 4 4 3 Basic Clock Module Registers 4 14 Chapter 4 ...

Page 114: ...in the 450 kHz to 8 MHz range XT2CLK Optional high frequency oscillator that can be used with standard crystals resonators or external clock sources in the 450 kHz to 8 MHz range DCOCLK Internal digitally controlled oscillator DCO with RC type characteristics Three clock signals are available from the basic clock module ACLK Auxiliary clock The ACLK is the buffered LFXT1CLK clock source divided by...

Page 115: ...vider 1 2 4 8 DIVMx SMCLK SCG1 DIVSx ACLK VCC Main System Clock Auxillary Clock Sub System Clock DCO DCOx MODx DC Generator SCG0 RSELx off SELS 1 0 SELMx 00 01 10 11 1 0 XT OSCOFF XTS LF XT 1 0 1 0 Divider 1 2 4 8 XT2CLK Modulator 1 0 n n 1 12pF 0 V LFOff XT1Off 0 V 12pF LFXT1CLK Note XT2 Oscillator The XT2 Oscillator is not present on MSP430x11xx or MSP430x12xx devices The LFXT1CLK is used in pla...

Page 116: ...for Low Power Applications Conflicting requirements typically exist in battery powered MSP430x1xx applications Low clock frequency for energy conservation and time keeping High clock frequency for fast reaction to events and fast burst processing capability The basic clock module addresses the above conflicting requirements by allowing the user to select from the three available clock signals ACLK...

Page 117: ...l clock signal on the XIN pin in either LF or HF mode When used with an external signal the external frequency must meet the datasheet parameters for the chosen mode Software can disable LFXT1 by setting OSCOFF if this signal does not source SMCLK or MCLK as shown in Figure 4 2 Figure 4 2 Off Signals for the LFXT1 Oscillator XT2 XTS OSCOFF CPUOFF SELM0 SELM1 SCG1 SELS XT2 is an Internal Signal XT2...

Page 118: ...FF SELM1 SELM0 SCG1 SELS XT2Off Internal signal 4 2 4 Digitally Controlled Oscillator DCO The DCO is an integrated ring oscillator with RC type characteristics As with any RC type oscillator frequency varies with temperature voltage and from device to device The DCO frequency can be adjusted by software using the DCOx MODx and RSELx bits The digital control of the oscillator allows frequency stabi...

Page 119: ...stor defines the fundamental frequency The DCOR bit selects the internal or external resistor The three RSELx bits select one of eight nominal frequency ranges for the DCO These ranges are defined for an individual device in the device specific data sheet The three DCOx bits divide the DCO range selected by the RSELx bits into 8 frequency steps separated by approximately 10 The five MODx bits swit...

Page 120: ...e coefficient to approximately 0 1 C See the device specific data sheet for parameters ROSC also allows the DCO to operate at higher frequencies For example the internal resistor nominal value is approximately 300 kΩ allowing the DCO to operate up to approximately 5 MHz When using an external ROSC of approximately 100 kΩ the DCO can operate up to approximately 10 MHz The user should take care to n...

Page 121: ...fDCO is lower than the effective frequency and fDCO 1 is higher than the effective frequency the error of the effective frequency integrates to zero It does not accumulate The error of the effective frequency is zero every 32 DCOCLK cycles Figure 4 7 illustrates the modulator operation The modulator settings and DCO control are configured with software The DCOCLK can be compared to a stable freque...

Page 122: ...NMI interrupt service routine can test the OFIFG flag to determine if an oscillator fault occurred The OFIFG flag must be cleared by software Note No Oscillator Fault Detection for LFXT1 in LF Mode Oscillator fault detection is only applicable for LFXT1 in HF mode and XT2 There is no oscillator fault detection for LFXT1 in LF mode OFIFG is set by the oscillator fault signal XT_OscFault XT_OscFault...

Page 123: ... is in LF mode and it remains cleared MCLK may be sourced by LFXT1CLK in LF mode regardless of the state of the OFIFG flag Figure 4 10 Oscillator Fault Interrupt XT_OscFault S Clear OFIFG OFIE PUC IRQA IE1 1 IFG1 1 XT1off LFXT1_OscFault POR XT2off XT2_OscFault XT2 Oscillator Fault Interrupt Request Fault_from XT2 Fault_from XT1 XTS SELM1 SELM0 DCOR Oscillator Fault Fail Safe Logic XT2 Is an intern...

Page 124: ...lock to the crystal clock LFXT1CLK or XT2CLK is 1 Switch on the crystal oscillator 2 Clear the OFIFG flag 3 Wait at least 50 µs 4 Test OFIFG and repeat steps 1 4 until OFIFG remains cleared Select LFXT1 HF mode for MCLK BIC OSCOFF SR Turn on osc BIS B XTS BCSCTL1 HF mode L1 BIC B OFIFG IFG1 Clear OFIFG MOV 0FFh R15 Delay L2 DEC R15 JNZ L2 BIT B OFIFG IFG1 Re test OFIFG JNZ L1 Repeat test if needed...

Page 125: ...ed to avoid critical race conditions as shown in Figure 4 11 1 The current clock cycle continues until the next rising edge 2 The clock remains high until the next rising edge of the new clock 3 The new clock source is selected and continues with a full high period Figure 4 11 Switch MCLK from DCOCLK to LFXT1CLK DCOCLK LFXT1CLK MCLK LFXT1CLK DCOCLK Select LFXT1CLK Wait for LFXT1CLK ...

Page 126: ... Register Short Form Register Type Address Initial State DCO control register DCOCTL Read write 056h 060h with PUC Basic clock system control 1 BCSCTL1 Read write 057h 084h with PUC Basic clock system control 2 BCSCTL2 Read write 058h Reset with POR SFR interrupt enable register 1 IE1 Read write 000h Reset with PUC SFR interrupt flag register 1 IFG1 Read write 002h Reset with PUC ...

Page 127: ...ency is used Not useable when DCOx 7 BCSCTL1 Basic Clock System Control Register 1 7 6 5 4 3 2 1 0 XT2OFF XTS DIVAx XT5V RSELx rw 1 rw 0 rw 0 rw 0 rw 0 rw 1 rw 0 rw 0 XT2OFF Bit 7 XT2 off This bit turns off the XT2 oscillator 0 XT2 is on 1 XT2 is off if it is not used for MCLK or SMCLK XTS Bit 6 LFXT1 mode select 0 Low frequency mode 1 High frequency mode DIVAx Bits 5 4 Divider for ACLK 00 1 01 2 ...

Page 128: ... 01 DCOCLK 10 XT2CLK when XT2 oscillator present on chip LFXT1CLK when XT2 oscillator not present on chip 11 LFXT1CLK DIVMx BitS 5 4 Divider for MCLK 00 1 01 2 10 4 11 8 SELS Bit 3 Select SMCLK This bit selects the SMCLK source 0 DCOCLK 1 XT2CLK when XT2 oscillator present on chip LFXT1CLK when XT2 oscillator not present on chip DIVSx BitS 2 1 Divider for SMCLK 00 1 01 2 10 4 11 8 DCOR Bit 0 DCO r...

Page 129: ...MOV B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled Bits 0 This bit may be used by other modules See device specific datasheet IFG1 Interrupt Flag Register 1 7 6 5 4 3 2 1 0 OFIFG rw 1 Bits 7 2 These bits may be used by other modules See device specific datasheet OFIFG Bit 1 Oscillator fault interrupt flag Because other bits in IFG1 may be used for other modules it is recommend...

Page 130: ...4 18 Basic Clock Module ...

Page 131: ...r This chapter describes the operation of the MSP430 flash memory controller Topic Page 5 1 Flash Memory Introduction 5 2 5 2 Flash Memory Segmentation 5 3 5 3 Flash Memory Operation 5 4 5 4 Flash Memory Registers 5 17 Chapter 5 ...

Page 132: ...nal programming voltage generation Bit byte or word programmable Ultralow power operation Segment erase and mass erase The block diagram of the flash memory and controller is shown in Figure 5 1 Note Minimum VCC During Flash Write or Erase The minimum VCC voltage during a flash write or erase operation is 2 7 V If VCC falls below 2 7 V during a write or erase the result of the write or erase will ...

Page 133: ...segments MSP430F1101 devices have only one The main memory has two or more 512 byte segments See the device specific datasheet for the complete memory map of a device The segments are further dividing into blocks A block is 64 bytes starting at 0xx00h 0xx40h 0xx80h or 0xxC0h and ending at 0xx3Fh 0xx7Fh 0xxBFh or 0xxFFh Figure 5 2 shows the flash segmentation using an example of 4 KB flash that has...

Page 134: ...uring the write or erase the code to be executed must be in RAM Any flash update can be initiated from within flash memory or RAM 5 3 1 Flash Memory Timing Generator Write and erase operations are controlled by the flash timing generator shown in Figure 5 3 The flash timing generator operating frequency f FTG must be in the range from 257 kHz to 476 kHz see device specific datasheet Figure 5 3 Fla...

Page 135: ...ely after the dummy write and remains set throughout the erase cycle BUSY MERAS and ERASE are automatically cleared when the cycle completes The erase cycle timing is not dependent on the amount of flash memory present on a device Erase cycle times are equivalent for all MSP430F1xx devices Figure 5 4 Erase Cycle Timing BUSY Erase Operation Active tAll Erase tMass Erase 5297 fFTG tSeg Erase 4819 fF...

Page 136: ...ible to erase the code needed for execution after the erase If this occurs CPU execution will be unpredictable after the erase cycle The flow to initiate an erase from flash is shown in Figure 5 5 Figure 5 5 Erase Cycle from Within Flash Memory Setup flash controller and erase mode Disable all interrupts and watchdog Set LOCK 1 re enable Interrupts and watchdog Dummy write Segment Erase from flash...

Page 137: ...e from flash from RAM is shown in Figure 5 6 Figure 5 6 Erase Cycle from Within RAM yes BUSY 1 yes BUSY 1 Disable all interrupts and watchdog Setup flash controller and erase mode Dummy write Set LOCK 1 re enable interrupts and watchdog Segment Erase from RAM 514 kHz SMCLK 952 kHz Assumes ACCVIE NMIIE OFIE 0 MOV WDTPW WDTHOLD WDTCTL Disable WDT DINT Disable interrupts L1 BIT BUSY FCTL3 Test BUSY J...

Page 138: ... access flash while BUSY 1 Otherwise an access violation occurs ACCVIFG is set and the flash write is unpredictable Byte Word Write A byte word write operation can be initiated from within flash memory or from RAM When initiating from within flash memory all timing is controlled by the flash controller and the CPU is held while the write completes After the write completes the CPU resumes code exe...

Page 139: ... specific datasheet for specifications Initiating a Byte Word Write from Within Flash Memory The flow to initiate a byte word write from flash is shown in Figure 5 8 Figure 5 8 Initiating a Byte Word Write from Flash Setup flash controller and set WRT 1 Disable all interrupts and watchdog Set WRT 0 LOCK 1 re enable interrupts and watchdog Write byte or word Byte word write from flash 514 kHz SMCLK...

Page 140: ... 0 LOCK 1 re enable interrupts and watchdog Byte word write from RAM 514 kHz SMCLK 952 kHz Assumes 0FF1Eh is already erased Assumes ACCVIE NMIIE OFIE 0 MOV WDTPW WDTHOLD WDTCTL Disable WDT DINT Disable interrupts L1 BIT BUSY FCTL3 Test BUSY JNZ L1 Loop while busy MOV FWKEY FSSEL1 FN0 FCTL2 SMCLK 2 MOV FWKEY FCTL3 Clear LOCK MOV FWKEY WRT FCTL1 Enable write MOV 0123h 0FF1Eh 0123h 0FF1Eh L2 BIT BUSY...

Page 141: ...d between writing each byte or word in the block When WAIT is set the next byte or word of the block can be written When writing successive blocks the BLKWRT bit must be cleared after the current block is complete BLKWRT can be set initiating the next block write after the required flash recovery time given by tEnd BUSY is cleared following each block write completion indicating the next block can...

Page 142: ...w is shown in Figure 5 8 and the following example Figure 5 11 Block Write Flow yes BUSY 1 Disable all interrupts and watchdog Setup flash controller Set BLKWRT WRT 1 Write byte or word no Block Border yes WAIT 0 yes BUSY 1 Set BLKWRT 0 yes Another Block Set WRT 0 LOCK 1 re enable interrupts and WDT ...

Page 143: ...le interrupts L1 BIT BUSY FCTL3 Test BUSY JNZ L1 Loop while busy MOV FWKEY FSSEL1 FN0 FCTL2 SMCLK 2 MOV FWKEY FCTL3 Clear LOCK MOV FWKEY BLKWRT WRT FCTL1 Enable block write L2 MOV Write_Value 0 R6 Write location L3 BIT WAIT FCTL3 Test WAIT JZ L3 Loop while WAIT 0 INCD R6 Point to next word DEC R5 Decrement write counter JNZ L2 End of block MOV FWKEY FCTL1 Clear WRT BLKWRT L4 BIT BUSY FCTL3 Test BU...

Page 144: ... CPU to fetch the proper op code and program execution resumes The flash access conditions while BUSY 1 are listed in Table 5 3 Table 5 3 Flash Access While BUSY 1 Flash Operation Flash Access WAIT Result Read 0 ACCVIFG 0 03FFFh is the value read Any erase or Byte word write Write 0 ACCVIFG 1 Write is ignored Any erase or Byte word write Instruction fetch 0 ACCVIFG 0 CPU fetches 03FFFh This is the...

Page 145: ...sets ACCVIFG Writing to FCTL1 is allowed in block write mode when WAIT 1 but writing to FCTL1 in block write mode when WAIT 0 is an access violation and sets ACCVIFG Any write to FCTL2 when the BUSY 1 is an access violation Any FCTLx register may be read when BUSY 1 A read will not cause an access violation 5 3 7 Flash Memory Controller Interrupts The flash controller has two interrupt sources KEY...

Page 146: ...sing a UART serial interface Access to the MSP430 flash memory via the BSL is protected by a 256 bit user defined password For more details see the Application report Features of the MSP430 Bootstrap Loader at www ti com sc msp430 Programming Flash Memory via a Custom Solution The ability of the MSP430 CPU to write to its own flash memory allows for in system and external custom programming soluti...

Page 147: ...ash Memory Registers Register Short Form Register Type Address Initial State Flash memory control register 1 FCTL1 Read write 0128h 09600h with PUC Flash memory control register 2 FCTL2 Read write 012Ah 09642h with PUC Flash memory control register 3 FCTL3 Read write 012Ch 09618h with PUC Interrupt Enable 1 IE1 Read write 000h Reset with PUC ...

Page 148: ... mode BLKWRT is automatically reset when EMEX is set 0 Block write mode is off 1 Block write mode is on WRT Bit 6 Write This bit is used to select any write mode WRT is automatically reset when EMEX is set 0 Write mode is off 1 Write mode is on Reserved Bits 5 3 Reserved Always read as 0 MERAS ERASE Bit 2 Bit 1 Mass erase and erase These bits are used together to select the erase mode MERAS and ER...

Page 149: ...0 rw 1 rw 0 FWKEYx Bits 15 8 FCTLx password Always read as 096h Must be written as 0A5h or a PUC will be generated FSSELx Bits 7 6 Flash controller clock source select 00 ACLK 01 MCLK 10 SMCLK 11 SMCLK FNx Bits 5 0 Flash controller clock divider These six bits select the divider for the flash controller clock The divisor value is FNx 1 For example when FNx 00h the divisor is 1 When FNx 03Fh the di...

Page 150: ...n and the operation will complete normally In the block write mode if the LOCK bit is set while BLKWRT WAIT 1 then BLKWRT and WAIT are reset and the mode ends normally 0 Unlocked 1 Locked WAIT Bit 3 Wait Indicates the flash memory is being written to 0 The flash memory is not ready for the next byte word write 1 The flash memory is ready for the next byte word write ACCVIFG Bit 2 Access violation ...

Page 151: ...er modules See device specific datasheet ACCVIE Bit 5 Flash memory access violation interrupt enable This bit enables the ACCVIFG interrupt Because other bits in IE1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled ...

Page 152: ...5 22 Flash Memory Controller ...

Page 153: ...ltage Supervisor This chapter describes the operation of the SVS The SVS is implemented in MSP430x15x and MSP430x16x devices Topic Page 6 1 SVS Introduction 6 2 6 2 SVS Operation 6 4 6 3 SVS Registers 6 7 Chapter 6 ...

Page 154: ...lag or generate a POR reset when the supply voltage or external voltage drops below a user selected threshold The SVS features include AVCC monitoring Selectable generation of POR Output of SVS comparator accessible by software Low voltage condition latched and accessible by software 14 selectable threshold levels External channel to monitor external voltage The SVS block diagram is shown in Figur...

Page 155: ...upply Voltage Supervisor Figure 6 1 SVS Block Diagram 1 25V Brownout Reset VCC Set SVSFG tReset 50us Reset SVSCTL Bits 0001 0010 0011 1111 1101 1100 G D S SVSOUT G D S VLD SVSON PORON SVSOP SVSFG 50us SVS_POR SVSIN AVCC AVCC ...

Page 156: ...SVS is on When VLDx 1111 the external SVSIN channel is selected The voltage on SVSIN is compared to an internal level of approximately 1 2 V 6 2 2 SVS Comparator Operation A low voltage condition exists when AVCC drops below the selected threshold or when the external voltage drops below its 1 2 V threshold Any low voltage condition sets the SVSFG bit The PORON bit enables or disables the device r...

Page 157: ...pproximately 50 µs The tsettle delay takes affect when the VLDx bits change from any non zero value to any other non zero value and is a maximum of 12 µs See the device specific datasheet for the delay parameters During the delays the SVS will not flag a low voltage condition or reset the device and the SVSON bit is cleared Software can test the SVSON bit to determine when the delay has elapsed an...

Page 158: ...se to the threshold The SVS operation and SVS Brownout interoperation are shown in Figure 6 3 Figure 6 3 Operating Levels for SVS and Brownout Reset Circuit V CC start AV CC V B_IT Brownout Region V SVSstart V SVS_IT td SVSR undefined Vhys SVS_IT 0 1 td BOR Brownout 0 1 td SVSon td BOR 0 1 Set POR Brown Out Region SVS Circuit Active SVSOUT Vhys B_IT Software Sets VLD 0 ...

Page 159: ...2 4 V 0110 2 5 V 0111 2 65 V 1000 2 8 V 1001 2 9 V 1010 3 05 1011 3 2 V 1100 3 35 V 1101 3 5 V 1110 3 7 V 1111 Compares external input voltage SVSIN to 1 2 V PORON Bit 3 POR on This bit enables the SVSFG flag to cause a POR device reset 0 SVSFG does not cause a POR 1 SVSFG causes a POR SVSON Bit 2 SVS on This bit reflects the status of SVS operation This bit DOES NOT turn on the SVS The SVS is tur...

Page 160: ...6 8 Supply Voltage Supervisor ...

Page 161: ...ribes the hardware multiplier The hardware multiplier is implemented in MSP430x14x and MSP430x16x devices Topic Page 7 1 Hardware Multiplier Introduction 7 2 7 2 Hardware Multiplier Operation 7 3 7 3 Hardware Multiplier Registers 7 7 Chapter 7 ...

Page 162: ...ructions The hardware multiplier supports Unsigned multiply Signed multiply Unsigned multiply accumulate Signed multiply accumulate 16 16 bits 16 8 bits 8 16 bits 8 8 bits The hardware multiplier block diagram is shown in Figure 7 1 Figure 7 1 Hardware Multiplier Block Diagram OP2 138h 16 x 16 Multipiler 32 bit Adder 32 bit Multiplexer 0 15 15 0 Multiplexer C MPY 130h MPYS 132h MAC 134h MACS 136h ...

Page 163: ...addressing for the result a NOP is required before the result is ready 7 2 1 Operand Registers The operand one register OP1 has four addresses shown in Table 7 1 used to select the multiply mode Writing the first operand to the desired address selects the type of multiply operation but does not start any operation Writing the second operand to the operand two register OP2 initiates the multiply op...

Page 164: ...MEXT contains the extended sign of the result 00000h Result was positive or zero 0FFFFh Result was negative MAC SUMEXT contains the carry of the result 0000h No carry for result 0001h Result has a carry MACS SUMEXT contains the extended sign of the result 00000h Result was positive or zero 0FFFFh Result was negative MACS Underflow and Overflow The multiplier does not automatically detect underflow...

Page 165: ...lts 8x8 Signed Multiply Absolute addressing MOV B 012h 0132h Load first operand SXT MPYS Sign extend first operand MOV B 034h 0138h Load 2nd operand SXT OP2 Sign extend 2nd operand triggers 2nd multiplication Process results 16x16 Unsigned Multiply Accumulate MOV 01234h MAC Load first operand MOV 05678h OP2 Load 2nd operand Process results 8x8 Unsigned Multiply Accumulate Absolute addressing MOV B...

Page 166: ...d 2nd operand NOP Need one cycle MOV R5 xxx Move RESLO MOV R5 xxx Move RESHI 7 2 5 Using Interrupts If an interrupt occurs after writing OP1 but before writing OP2 and the multiplier is used in servicing that interrupt the original multiplier mode selection is lost and the results are unpredictable To avoid this disable interrupts before using the hardware multiplier or do not use the multiplier i...

Page 167: ...te Operand one multiply MPY Read write 0130h Unchanged Operand one signed multiply MPYS Read write 0132h Unchanged Operand one multiply accumulate MAC Read write 0134h Unchanged Operand one signed multiply accumulate MACS Read write 0136h Unchanged Operand two OP2 Read write 0138h Unchanged Result low word RESLO Read write 013Ah Undefined Result high word RESHI Read write 013Ch Undefined Sum Exten...

Page 168: ...7 8 Hardware Multiplier ...

Page 169: ...ess to another without CPU intervention This chapter describes the operation of the DMA controller The DMA controller is implemented in MSP430x15x and MSP430x16x devices Topic Page 8 1 DMA Introduction 8 2 8 2 DMA Operation 8 4 8 3 DMA Registers 8 18 Chapter 8 ...

Page 170: ...sumption by allowing the CPU to remain in a low power mode without having to awaken to move data to or from a peripheral The DMA controller features include Three independent transfer channels Configurable DMA channel priorities Requires only two MCLK clock cycles Byte or word and mixed byte word transfer capability Block sizes up to 65535 bytes or words Configurable transfer trigger selections Se...

Page 171: ...RT1 transmit ready USART1 data received DMAE0 4 DMA0IFG 0000 0001 0010 0011 0100 0101 1111 1110 0110 0111 1000 1001 1010 DMAE0 4 DMA1IFG 0000 0001 0010 0011 0100 0101 1111 1110 0110 0111 1000 1001 1010 0000 0001 0010 0011 0100 0101 1111 1110 0110 0111 1000 1001 1010 Multiplier ready No trigger No trigger DAC12_0IFG DMAREQ TACCR2_CCIFG TBCCR2_CCIFG USART0 data received USART0 transmit ready USART1 ...

Page 172: ...odes are configured with the DMASRCINCRx and DMADSTINCRx control bits The DMASRCINCRx bits select if the source address is incremented decremented or unchanged after each transfer The DMADSTINCRx bits select if the destination address is incremented decremented or unchanged after each transfer Transfers may be byte to byte word to word byte to word or word to byte When transferring word to byte on...

Page 173: ...Transfer Mode Description 000 Single transfer Each transfer requires a trigger DMAEN is automatically cleared when DMAxSZ transfers have been made 001 Block transfer A complete block is transferred with one trigger DMAEN is automatically cleared at the end of the block transfer 010 011 Burst block transfer CPU activity is interleaved with a block transfer DMAEN is automatically cleared at the end ...

Page 174: ...xSA DMAxDA and DMAxSZ registers are copied into temporary registers The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer The DMAxSZ register is decremented after each transfer When the DMAxSZ register decrements to zero it is reloaded from its temporary register and the corresponding DMAIFG flag is set When DMADTx 0 the DMAEN bit is cleared automatically whe...

Page 175: ...MAABORT 1 2 x MCLK DMAEN 0 Modify T_SourceAdd Modify T_DestAdd Decrement DMAxSZ ENNMI 1 AND NMI event OR DMALEVEL 1 AND Trigger 0 DMADTx 0 AND DMAxSZ 0 OR DMAEN 0 DMAxSZ T_Size DMAxSA T_SourceAdd DMAxDA T_DestAdd DMAREQ 0 DMAxSZ 0 AND DMAEN 1 DMAEN 0 DMAEN 1 T_Size DMAxSZ DMAxSA T_SourceAdd DMAxDA T_DestAdd DMADTx 4 AND DMAxSZ 0 AND DMAEN 1 DMAEN 0 DMAREQ 0 T_Size DMAxSZ ...

Page 176: ... occur The DMAxSA DMAxDA and DMAxSZ registers are copied into temporary registers The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block The DMAxSZ register is decremented after each transfer of the block and shows the number of transfers remaining in the block When the DMAxSZ register decrements to zero it is reloaded from its temporary register ...

Page 177: ...RT 0 DMAABORT 1 2 x MCLK DMAEN 0 Modify T_SourceAdd Modify T_DestAdd Decrement DMAxSZ DMAxSZ 0 ENNMI 1 AND NMI event OR DMALEVEL 1 AND Trigger 0 DMADTx 1 AND DMAxSZ 0 OR DMAEN 0 DMAxSZ T_Size DMAxSA T_SourceAdd DMAxDA T_DestAdd DMAREQ 0 T_Size DMAxSZ DMAxSA T_SourceAdd DMAxDA T_DestAdd DMADTx 5 AND DMAxSZ 0 AND DMAEN 1 DMAEN 0 DMAEN 1 DMAEN 0 DMAREQ 0 T_Size DMAxSZ ...

Page 178: ...r of the block If DMAxSZ 0 no transfers occur The DMAxSA DMAxDA and DMAxSZ registers are copied into temporary registers The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block The DMAxSZ register is decremented after each transfer of the block and shows the number of transfers remaining in the block When the DMAxSZ register decrements to zero it i...

Page 179: ...RT 0 DMAABORT 1 2 x MCLK DMAEN 0 Modify T_SourceAdd Modify T_DestAdd Decrement DMAxSZ DMADTx 6 7 AND DMAxSZ 0 ENNMI 1 AND NMI event OR DMALEVEL 1 AND Trigger 0 DMADTx 2 3 AND DMAxSZ 0 OR DMAEN 0 DMAxSZ T_Size DMAxSA T_SourceAdd DMAxDA T_DestAdd T_Size DMAxSZ DMAxSA T_SourceAdd DMAxDA T_DestAdd DMAEN 0 DMAEN 1 DMAxSZ 0 DMAxSZ 0 AND a multiple of 4 words bytes were transferred DMAxSZ 0 DMAEN 0 DMARE...

Page 180: ...ger DMA transfers are triggered as long as the trigger signal is high and the DMAEN bit remains set The trigger signal must remain high for a block or burst block transfer to complete If the trigger signal goes low during a block or burst block transfer the DMA controller is held in its current state until the trigger goes back high or until the DMA registers are modified by software If the DMA re...

Page 181: ...L DAC12IFG flag is set The DAC12_0CTL DAC12IFG flag is automatically cleared when the transfer starts If the DAC12_0CTL DAC12IE bit is set the DAC12_0CTL DAC12IFG flag will not trigger a transfer 0110 A transfer is triggered by an ADC12IFGx flag When single channel conversions are performed the corresponding ADC12IFGx is the trigger When sequences are used the ADC12IFGx for the last conversion in ...

Page 182: ... the second priority channel then the third priority channel Transfers in progress are not halted if a higher priority channel is triggered The higher priority channel waits until the transfer in progress completes before starting The DMA channel priorities are configurable with the ROUNDROBIN bit When the ROUNDROBIN bit is set the channel that completes a transfer becomes the lowest priority The ...

Page 183: ...ller will temporarily restart MCLK sourced with DCOCLK for the single transfer or complete block or burst block transfer The CPU remains off and after the transfer completes MCLK is turned off The maximum DMA cycle time for all operating modes is shown in Table 8 3 Table 8 3 Maximum Single Transfer DMA Cycle Time CPU Operating Mode Clock Source Maximum DMA Cycle Time Active mode MCLK DCOCLK 4 MCLK...

Page 184: ... DMA controller should be disabled prior to executing the routine 8 2 8 DMA Controller Interrupts Each DMA channel has its own DMAIFG flag Each DMAIFG flag is set in any mode when the corresponding DMAxSZ register counts to zero If the corresponding DMAIE and GIE bits are set an interrupt request is generated All DMAIFG flags source only one DMA controller interrupt vector and the interrupt vector...

Page 185: ...o remain off while data transfers occur DMA transfers can be triggered from any ADC12IFGx flag When CONSEQx 0 2 the ADC12IFGx flag for the ADC12MEMx used for the conversion can trigger a DMA transfer When CONSEQx 1 3 the ADC12IFGx flag for the last ADC12MEMx in the sequence can trigger a DMA transfer Any ADC12IFGx flag is automatically cleared when the DMA controller accesses the corresponding ADC...

Page 186: ...ess DMA0DA Read write 01E4h Unchanged DMA channel 0 transfer size DMA0SZ Read write 01E6h Unchanged DMA channel 1 control DMA1CTL Read write 01E8h Reset with POR DMA channel 1 source address DMA1SA Read write 01EAh Unchanged DMA channel 1 destination address DMA1DA Read write 01ECh Unchanged DMA channel 1 transfer size DMA1SZ Read write 01EEh Unchanged DMA channel 2 control DMA2CTL Read write 01F0...

Page 187: ...CR2 CCIFG bit 0010 TBCCR2 CCIFG bit 0011 URXIFG0 UART SPI mode USART0 data received I2C mode 0100 UTXIFG0 UART SPI mode USART0 transmit ready I2C mode 0101 DAC12_0CTL DAC12IFG bit 0110 ADC12 ADC12IFGx bit 0111 TACCR0 CCIFG bit 1000 TBCCR0 CCIFG bit 1001 URXIFG1 bit 1010 UTXIFG1 bit 1011 Multiplier ready 1100 No action 1101 No action 1110 DMA0IFG bit triggers DMA channel 1 DMA1IFG bit triggers DMA ...

Page 188: ...on next instruction fetch after the trigger ROUND ROBIN Bit 1 Round robin This bit enables the round robin DMA channel priorities 0 DMA channel priority is DMA0 DMA1 DMA2 1 DMA channel priority changes with each transfer ENNMI Bit 0 Enable NMI This bit enables the interruption of a DMA transfer by an NMI interrupt When an NMI interrupts a DMA transfer the current transfer is completed normally fur...

Page 189: ...e destination address increments decrements by two The DMAxDA is copied into a temporary register and the temporary register is incremented or decremented DMAxDA is not incremented or decremented 00 Destination address is unchanged 01 Destination address is unchanged 10 Destination address is decremented 11 Destination address is incremented DMA SRCINCRx Bits 9 8 DMA source increment This bit sele...

Page 190: ... DMA Abort This bit indicates if a DMA transfer was interrupt by an NMI 0 DMA transfer not interrupted 1 DMA transfer was interrupted by NMI DMAREQ Bit 0 DMA request Software controlled DMA start DMAREQ is reset automatically 0 No DMA start 1 Start DMA DMAxSA DMA Source Address Register 15 14 13 12 11 10 9 8 DMAxSAx rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 DMAxSAx rw rw rw rw rw rw rw rw DMAxSAx Bi...

Page 191: ... block transfers DMAxSZ DMA Size Address Register 15 14 13 12 11 10 9 8 DMAxSZx rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 DMAxSZx rw rw rw rw rw rw rw rw DMAxSZx Bits 15 0 DMA size The DMA size register defines the number of byte word data per block transfer DMAxSZ register decrements with each word or byte transfer When DMAxSZ decrements to 0 it is immediately and automatically reloaded with its pr...

Page 192: ...8 24 ...

Page 193: ... are implemented in MSP430x11xx devices Ports P1 P3 are implemented in MSP430x12xx devices Ports P1 P6 are implemented in MSP430x13x MSP430x14x MSP430x15x and MSP430x16x devices Topic Page 9 1 Digital I O Introduction 9 2 9 2 Digital I O Operation 9 3 9 3 Digital I O Registers 9 7 Chapter 9 ...

Page 194: ... P2 have interrupt capability Each interrupt for the P1 and P2 I O lines can be individually enabled and configured to provide an interrupt on a rising edge or falling edge of an input signal All P1 I O lines source a single interrupt vector and all P2 I O lines source a different single interrupt vector The digital I O features include Independently programmable individual I Os Any combination of...

Page 195: ...ers results in increased current consumption while the write attempt is active 9 2 2 Output Registers PxOUT Each bit in each PxOUT register is the value to be output on the corresponding I O pin when the pin is configured as I O function and output direction Bit 0 The output is low Bit 1 The output is high 9 2 3 Direction Registers PxDIR Each bit in each PxDIR register selects the direction of the...

Page 196: ...chematics in the device specific datasheet Output ACLK on P2 0 on MSP430F11x1 BIS B 01h P2SEL Select ACLK function for pin BIS B 01h P2DIR Set direction to output Required Note P1 and P2 Interrupts Are Disabled When PxSEL 1 When any P1SELx or P2SELx bit is set the corresponding pin s interrupt function is disabled Therefore signals on these pins will not generate P1 or P2 interrupts regardless of ...

Page 197: ...Each PxIFG flag must be reset with software Software can also set each PxIFG flag providing a way to generate a software initiated interrupt Bit 0 No interrupt is pending Bit 1 An interrupt is pending Only transitions not static levels cause interrupts If any PxIFGx flag becomes set during a Px interrupt service routine or is set after the RETI instruction of a Px interrupt service routine is exec...

Page 198: ...upt flags PxIESx PxINx PxIFGx 0 1 0 May be set 0 1 1 Unchanged 1 0 0 Unchanged 1 0 1 May be set Interrupt Enable P1IE P2IE Each PxIE bit enables the associated PxIFG interrupt flag Bit 0 The interrupt is disabled Bit 1 The interrupt is enabled 9 2 6 Configuring Unused Port Pins Unused I O pins should be configured as I O function output direction and left unconnected on the PC board to reduce powe...

Page 199: ...P2DIR 02Ah Read write Reset with PUC Interrupt Flag P2IFG 02Bh Read write Reset with PUC Interrupt Edge Select P2IES 02Ch Read write Unchanged Interrupt Enable P2IE 02Dh Read write Reset with PUC Port Select P2SEL 02Eh Read write Reset with PUC P3 Input P3IN 018h Read only P3 Output P3OUT 019h Read write Unchanged Direction P3DIR 01Ah Read write Reset with PUC Port Select P3SEL 01Bh Read write Res...

Page 200: ...9 8 Digital I O ...

Page 201: ...ed as a watchdog or as an interval timer This chapter describes the watchdog timer The watchdog timer is implemented in all MSP430x1xx devices Topic Page 10 1 Watchdog Timer Introduction 10 2 10 2 Watchdog Timer Operation 10 4 10 2 Watchdog Timer Registers 10 7 Chapter 10 ...

Page 202: ...e interrupts at selected time intervals Features of the watchdog timer module include Four software selectable time intervals Watchdog mode Interval mode Access to WDT control register is password protected Control of RST NMI pin function Selectable clock source Can be stopped to conserve power The WDT block diagram is shown in Figure 10 1 Note Watchdog Timer Powers Up Active After a PUC the WDT m...

Page 203: ...ck Diagram WDTQn Y 1 2 3 4 Q6 Q9 Q13 Q15 16 bit Counter CLK A B 1 1 A EN PUC SMCLK ACLK Clear Password Compare 0 0 0 0 1 1 1 1 WDTCNTCL WDTTMSEL WDTNMI WDTNMIES WDTIS1 WDTSSEL WDTIS0 WDTHOLD EQU EQU Write Enable Low Byte R W MDB LSB MSB WDTCTL Asyn Int Flag Pulse Generator 16 bit ...

Page 204: ...e user must setup halt or clear the WDT prior to the expiration of the initial reset interval or another PUC will be generated When the WDT is configured to operate in watchdog mode either writing to WDTCTL with an incorrect password or expiration of the selected time interval triggers a PUC A PUC resets the WDT to its default condition and configures the RST NMI pin to reset mode 10 2 3 Interval ...

Page 205: ...caused the device to reset If the flag is set then the watchdog timer initiated the reset condition either by timing out or by a security key violation If WDTIFG is cleared the reset was caused by a different source When using the WDT in interval timer mode the WDTIFG flag is set after the selected time interval and requests a WDT interval timer interrupt if the WDTIE and the GIE bits are set The ...

Page 206: ...ce if the user wants to use low power mode 3 because SMCLK is not active in LPM3 and the WDT would not function When the watchdog timer is not required the WDTHOLD bit can be used to hold the WDTCNT reducing power consumption 10 2 6 Software Examples Any write operation to WDTCTL must be a word operation with 05Ah WDTPW in the upper byte Periodically clear an active watchdog MOV WDTPW WDTCNTCL WDT...

Page 207: ...e 10 1 Table 10 1 Watchdog Timer Registers Register Short Form Register Type Address Initial State Watchdog timer control register WDTCTL Read write 0120h 06900h with PUC SFR interrupt enable register 1 IE1 Read write 0000h Reset with PUC SFR interrupt flag register 1 IFG1 Read write 0002h Reset with PUC WDTIFG is reset with POR ...

Page 208: ... interrupt when WDTNMI 1 Modifying this bit can trigger an NMI Modify this bit when WDTNMI 0 to avoid triggering an accidental NMI 0 NMI on rising edge 1 NMI on falling edge WDTNMI Bit 5 Watchdog timer NMI select This bit selects the function for the RST NMI pin 0 Reset function 1 NMI function WDTTMSEL Bit 4 Watchdog timer mode select 0 Watchdog mode 1 Interval timer mode WDTCNTCL Bit 3 Watchdog t...

Page 209: ... BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled Bits 3 1 These bits may be used by other modules See device specific datasheet WDTIE Bit 0 Watchdog timer interrupt enable This bit enables the WDTIFG interrupt for interval timer mode It is not necessary to set this bit for watchdog mode Because other bits in IE1 may be used for other ...

Page 210: ...ctions rather than MOV B or CLR B instructions 0 No interrupt pending 1 Interrupt pending Bits 3 1 These bits may be used by other modules See device specific datasheet WDTIFG Bit 0 Watchdog timer interrupt flag In watchdog mode WDTIFG remains set until reset by software In interval mode WDTIFG is reset automatically by servicing the interrupt or can be reset by software Because other bits in IFG1...

Page 211: ...er counter with three capture compare registers This chapter describes Timer_A Timer_A is implemented in all MSP430x1xx devices Topic Page 11 1 Timer_A Introduction 11 2 11 2 Timer_A Operation 11 4 11 3 Timer_A Registers 11 19 Chapter 11 ...

Page 212: ...Asynchronous 16 bit timer counter with four operating modes Selectable and configurable clock source Three configurable capture compare registers Configurable outputs with PWM capability Asynchronous input and output latching Interrupt vector register for fast decoding of all Timer_A interrupts The block diagram of Timer_A is shown in Figure 11 1 Note Use of the Word Count Count is used throughout...

Page 213: ... logic Output Unit2 D Set Q EQU0 OUT OUT2 Signal Reset GND VCC CCI2A CCI2B EQU2 Divider 1 2 4 8 Count Mode 16 bit Timer TAR RC ACLK SMCLK TACLK INCLK Set TAIFG 15 0 TASSELx MCx IDx 00 01 10 11 Clear Timer Clock EQU0 Timer Clock Timer Clock SCCI Y A EN CCR1 POR TACLR CCR0 Timer Block 00 01 10 11 CAP 1 0 1 0 CCR2 Set TACCR2 CCIFG TACCR2 ...

Page 214: ...is recommended to stop the timer before modifying its operation with exception of the interrupt enable interrupt flag and TACLR to avoid errant operating conditions When the TACLK is asynchronous to the CPU clock any read from TAR should occur while the timer is not operating or the results may be unpredictable Alternatively the timer may be read multiple times while operating and a majority vote ...

Page 215: ...this scenario the timer starts incrementing in the up direction from zero 11 2 3 Timer Mode Control The timer has four modes of operation as described in Table 11 1 stop up continuous and up down The operating mode is selected with the MCx bits Table 11 1 Timer Modes MCx Mode Description 00 Stop The timer is halted 01 Up The timer repeatedly counts from zero to the value of TACCR0 10 Continuous Th...

Page 216: ...ode 0h 0FFFFh TACCR0 The TACCR0 CCIFG interrupt flag is set when the timer counts to the TACCR0 value The TAIFG interrupt flag is set when the timer counts from TACCR0 to zero Figure 11 3 shows the flag set cycle Figure 11 3 Up Mode Flag Setting CCR0 1 CCR0 0h Timer Clock Timer Set TAIFG Set TACCR0 CCIFG 1h CCR0 1 CCR0 0h Changing the Period Register TACCR0 When changing TACCR0 while the timer is ...

Page 217: ...re 11 4 The capture compare register TACCR0 works the same way as the other capture compare registers Figure 11 4 Continuous Mode 0h 0FFFFh The TAIFG interrupt flag is set when the timer counts from 0FFFFh to zero Figure 11 5 shows the flag set cycle Figure 11 5 Continuous Mode Flag Setting FFFEh FFFFh 0h Timer Clock Timer Set TAIFG 1h FFFEh FFFFh 0h ...

Page 218: ... software without impact from interrupt latency Up to three independent time intervals or output frequencies can be generated using all three capture compare registers Figure 11 6 Continuous Mode Time Intervals 0FFFFh TACCR0a TACCR0b TACCR0c TACCR0d t1 t0 t0 TACCR1a TACCR1b TACCR1c TACCR1d t1 t1 t0 Time intervals can be produced with other modes as well where TACCR0 is used as the period register ...

Page 219: ...in the same direction it was counting before it was stopped If this is not desired the TACLR bit must be set to clear the direction The TACLR bit also clears the TAR value and the TACLK divider In up down mode the TACCR0 CCIFG interrupt flag and the TAIFG interrupt flag are set only once during a period separated by 1 2 the timer period The TACCR0 CCIFG interrupt flag is set when the timer counts ...

Page 220: ...unter begins counting down Use of the Up Down Mode The up down mode supports applications that require dead times between output signals See section Timer_A Output Unit For example to avoid overload conditions two outputs driving an H bridge must never be in a high state simultaneously In the example shown in Figure 11 9 the tdead is tdead ttimer TACCR1 TACCR2 With tdead Time during which both out...

Page 221: ... register The interrupt flag CCIFG is set The input signal level can be read at any time via the CCI bit MSP430x1xx family devices may have different signals connected to CCIxA and CCIxB Refer to the device specific datasheet for the connections of these signals The capture signal can be asynchronous to the timer clock and cause a race condition Setting the SCS bit will synchronize the capture wit...

Page 222: ...s Software then sets CCIS1 1 and toggles bit CCIS0 to switch the capture signal between VCC and GND initiating a capture each time CCIS0 changes state MOV CAP SCS CCIS1 CM_3 TACCTLx Setup TACCTLx XOR CCIS0 TACCTLx TACCTLx TAR Compare Mode The compare mode is selected when CAP 0 The compare mode is used to generate PWM output signals or interrupts at specific time intervals When TAR counts to the v...

Page 223: ...n the timer counts to the TACCRx value It remains set until a reset of the timer or until another output mode is selected and affects the output 010 Toggle Reset The output is toggled when the timer counts to the TACCRx value It is reset when the timer counts to the TACCR0 value 011 Set Reset The output is set when the timer counts to the TACCRx value It is reset when the timer counts to the TACCR...

Page 224: ...nding on the output mode An example is shown in Figure 11 12 using TACCR0 and TACCR1 Figure 11 12 Output Example Timer in Up Mode 0h 0FFFFh EQU0 TAIFG Output Mode 1 Set Output Mode 2 Toggle Reset Output Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set TACCR0 TACCR1 EQU1 EQU0 TAIFG EQU1 EQU0 TAIFG Interrupt Events ...

Page 225: ...on the output mode An example is shown in Figure 11 13 using TACCR0 and TACCR1 Figure 11 13 Output Example Timer in Continuous Mode 0h 0FFFFh TAIFG Output Mode 1 Set Output Mode 2 Toggle Reset Output Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set TACCR0 TACCR1 EQU1 TAIFG EQU1 EQU0 Interrupt Events EQU0 ...

Page 226: ... Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set TACCR0 TACCR2 EQU2 TAIFG Interrupt Events EQU2 EQU0 EQU2 EQU2 EQU0 Note Switching Between Output Modes When switching between output modes one of the OUTMODx bits should remain set during the transition unless switching to mode 0 Otherwise output glitching can occur because a NOR gate decode...

Page 227: ...set Timer Clock POR CAP EQU0 Capture IRACC Interrupt Request Accepted CCIE TAIV Interrupt Vector Generator The TACCR1 CCIFG TACCR2 CCIFG and TAIFG flags are prioritized and combined to source a single interrupt vector The interrupt vector register TAIV is used to determine which flag requested an interrupt The highest priority enabled interrupt generates a number in the TAIV register see register ...

Page 228: ...pture compare block TACCR0 11 cycles Capture compare blocks TACCR1 TACCR2 16 cycles Timer overflow TAIFG 14 cycles Interrupt handler for TACCR0 CCIFG Cycles CCIFG_0_HND Start of handler Interrupt latency 6 RETI 5 Interrupt handler for TAIFG TACCR1 and TACCR2 CCIFG TA_HND Interrupt latency 6 ADD TAIV PC Add offset to Jump table ā3 RETI Vector 0 No interrupt 5 JMP CCIFG_1_HND Vector 2 TACCR1 2 JMP C...

Page 229: ...with POR Timer_A capture compare control 0 TACCTL0 Read write 0162h Reset with POR Timer_A capture compare 0 TACCR0 Read write 0172h Reset with POR Timer_A capture compare control 1 TACCTL1 Read write 0164h Reset with POR Timer_A capture compare 1 TACCR1 Read write 0174h Reset with POR Timer_A capture compare control 2 TACCTL2 Read write 0166h Reset with POR Timer_A capture compare 2 TACCR2 Read w...

Page 230: ...4 Mode control Setting MCx 00h when Timer_A is not in use conserves power 00 Stop mode the timer is halted 01 Up mode the timer counts up to TACCR0 10 Continuous mode the timer counts up to 0FFFFh 11 Up down mode the timer counts up to TACCR0 then down to 0000h Unused Bit 3 Unused TACLR Bit 2 Timer_A clear Setting this bit resets TAR the TACLK divider and the count direction The TACLR bit is autom...

Page 231: ...mer_A TAR Timer_A Register 15 14 13 12 11 10 9 8 TARx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 TARx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 TARx Bits 15 0 Timer_A register The TAR register is the count of Timer_A ...

Page 232: ...vice specific datasheet for specific signal connections 00 CCIxA 01 CCIxB 10 GND 11 VCC SCS Bit 11 Synchronize capture source This bit is used to synchronize the capture input signal with the timer clock 0 Asynchronous capture 1 Synchronous capture SCCI Bit 10 Synchronized capture compare input The selected CCI input signal is latched with the EQUx signal and can be read via this bit Unused Bit 9 ...

Page 233: ...ow occurred COV must be reset with software 0 No capture overflow occurred 1 Capture overflow occurred CCIFG Bit 0 Capture compare interrupt flag 0 No interrupt pending 1 Interrupt pending TAIV Timer_A Interrupt Vector Register 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 0 0 0 TAIVx 0 r0 r0 r0 r0 r 0 r 0 r 0 r0 TAIVx Bits 15 0 Timer_A Interrupt Vector value TAIV...

Page 234: ...11 24 Timer_A ...

Page 235: ...bes Timer_B Timer_B3 three capture compare registers is implemented in MSP430x13x and MSP430x15x devices Timer_B7 seven capture compare registers is implemented in MSP430x14x and MSP430x16x devices Topic Page 12 1 Timer_B Introduction 12 2 12 2 Timer_B Operation 12 4 12 3 Timer_B Registers 12 20 Chapter 12 ...

Page 236: ...tputs with PWM capability Double buffered compare latches with synchronized loading Interrupt vector register for fast decoding of all Timer_B interrupts The block diagram of Timer_B is shown in Figure 12 1 Note Use of the Word Count Count is used throughout this chapter It means the counter must be in the process of counting for the action to take place If a particular value is directly written t...

Page 237: ...unt Mode 16 bit Timer TBR Set TBIFG 15 0 MCx IDx Clear TBCLR Timer Clock CCR0 EQU0 Timer Clock Timer Clock VCC TBR 0 UP DOWN EQU0 CLLDx CNTLx Load CCR1 CCR2 CCR3 CCR4 CCR5 Timer Block TBCCR6 RC 10 12 16 8 TBCLGRPx CCR5 CCR4 CCR1 Group Load Logic Group Load Logic TBSSELx 00 01 10 11 GND VCC CCI6A CCI6B 00 01 10 11 CCISx 00 01 10 11 00 01 10 11 CAP 1 0 SCS 1 0 Set TBCCR6 CCIFG Compare Latch TBCL6 AC...

Page 238: ...rating conditions When the TBCLK is asynchronous to the CPU clock any read from TBR should occur while the timer is not operating or the results may be unpredictable Alternatively the timer may be read multiple times while operating and a majority vote taken in software to determine the correct reading Any write to TBR will take effect immediately TBR Length Timer_B is configurable to operate as a...

Page 239: ...ts incrementing in the up direction from zero 12 2 3 Timer Mode Control The timer has four modes of operation as described in Table 12 1 stop up continuous and up down The operating mode is selected with the MCx bits Table 12 1 Timer Modes MCx Mode Description 00 Stop The timer is halted 01 Up The timer repeatedly counts from zero to the value of compare register TBCL0 10 Continuous The timer repe...

Page 240: ... TBCCR0 CCIFG interrupt flag is set when the timer counts to the TBCL0 value The TBIFG interrupt flag is set when the timer counts from TBCL0 to zero Figure 11 3 shows the flag set cycle Figure 12 3 Up Mode Flag Setting TBCL0 1 TBCL0 0h Timer Clock Timer Set TBIFG Set TBCCR0 CCIFG 1h TBCL0 1 TBCL0 0h Changing the Period Register TBCL0 When changing TBCL0 while the timer is running and when the TBC...

Page 241: ...12 4 The compare latch TBCL0 works the same way as the other capture compare registers Figure 12 4 Continuous Mode 0h TBR max The TBIFG interrupt flag is set when the timer counts from TBR max to zero Figure 12 5 shows the flag set cycle Figure 12 5 Continuous Mode Flag Setting TBR max 1 TBR max 0h Timer Clock Timer Set TBIFG 1h TBR max 0h TBR max 1 ...

Page 242: ...errupt latency Up to three Timer_B3 or 7 Timer_B7 independent time intervals or output frequencies can be generated using capture compare registers Figure 12 6 Continuous Mode Time Intervals 0h EQU0 Interrupt TBCL0a TBCL0b TBCL0c TBCL0d t1 t0 t0 TBCL1a TBCL1b TBCL1c TBCL1d t1 t1 t0 EQU1 Interrupt TBR max Time intervals can be produced with other modes as well where TBCL0 is used as the period regi...

Page 243: ...latched This allows the timer to be stopped and then restarted in the same direction it was counting before it was stopped If this is not desired the TBCLR bit must be used to clear the direction The TBCLR bit also clears the TBR value and the TBCLK divider In up down mode the TBCCR0 CCIFG interrupt flag and the TBIFG interrupt flag are set only once during the period separated by 1 2 the timer pe...

Page 244: ...L0 is loaded the timer begins counting down However one additional count may occur before the counter begins counting down Use of the Up Down Mode The up down mode supports applications that require dead times between output signals see section Timer_B Output Unit For example to avoid overload conditions two outputs driving an H bridge must never be in a high state simultaneously In the example sh...

Page 245: ... TBCCRx register The interrupt flag CCIFG is set The input signal level can be read at any time via the CCI bit MSP430x1xx family devices may have different signals connected to CCIxA and CCIxB Refer to the device specific datasheet for the connections of these signals The capture signal can be asynchronous to the timer clock and cause a race condition Setting the SCS bit will synchronize the capt...

Page 246: ...r capture on both edges Software then sets bit CCIS1 1 and toggles bit CCIS0 to switch the capture signal between VCC and GND initiating a capture each time CCIS0 changes state MOV CAP SCS CCIS1 CM_3 TBCCTLx Setup TBCCTLx XOR CCIS0 TBCCTLx TBCCTLx TBR Compare Mode The compare mode is selected when CAP 0 Compare mode is used to generate PWM output signals or interrupts at specific time intervals Wh...

Page 247: ... mode 11 New data is transferred from TBCCRx to TBCLx when TBR counts to the old TBCLx value Grouping Compare Latches Multiple compare latches may be grouped together for simultaneous updates with the TBCLGRPx bits When using groups the CLLDx bits of the lowest numbered TBCCRx in the group determine the load event for each compare latch of the group except when TBCLGRP 3 as shown in Table 12 3 The...

Page 248: ...OUTx is defined by the OUTx bit The OUTx signal updates immediately when OUTx is updated 001 Set The output is set when the timer counts to the TBCLx value It remains set until a reset of the timer or until another output mode is selected and affects the output 010 Toggle Reset The output is toggled when the timer counts to the TBCLx value It is reset when the timer counts to the TBCL0 value 011 S...

Page 249: ...nding on the output mode An example is shown in Figure 12 12 using TBCL0 and TBCL1 Figure 12 12 Output Example Timer in Up Mode 0h TBR max EQU0 TBIFG Output Mode 1 Set Output Mode 2 Toggle Reset Output Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set TBCL0 TBCL1 EQU1 EQU0 TBIFG EQU1 EQU0 TBIFG Interrupt Events ...

Page 250: ...on the output mode An example is shown in Figure 12 13 using TBCL0 and TBCL1 Figure 12 13 Output Example Timer in Continuous Mode 0h TBR max TBIFG Output Mode 1 Set Output Mode 2 Toggle Reset Output Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set TBCL0 TBCL1 EQU1 TBIFG EQU1 EQU0 Interrupt Events EQU0 ...

Page 251: ...Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set TBCL0 TBCL3 EQU3 TBIFG Interrupt Events EQU3 EQU0 EQU3 EQU3 EQU0 Note Switching Between Output Modes When switching between output modes one of the OUTMODx bits should remain set during the transition unless switching to mode 0 Otherwise output glitching can occur because a NOR gate decodes o...

Page 252: ... POR CAP EQU0 Capture IRACC Interrupt Request Accepted CCIE TBIV Interrupt Vector Generator The TBIFG flag and TBCCRx CCIFG flags excluding TBCCR0 CCIFG are prioritized and combined to source a single interrupt vector The interrupt vector register TBIV is used to determine which flag requested an interrupt The highest priority enabled interrupt excluding TBCCR0 CCIFG generates a number in the TBIV...

Page 253: ...owing software example shows the recommended use of TBIV for Timer_B3 Interrupt handler for TBCCR0 CCIFG Cycles CCIFG_0_HND Start of handler Interrupt latency 6 RETI 5 Interrupt handler for TBIFG TBCCR1 and TBCCR2 CCIFG TB_HND Interrupt latency 6 ADD TBIV PC Add offset to Jump table ā3 RETI Vector 0 No interrupt 5 JMP CCIFG_1_HND Vector 2 Module 1 2 JMP CCIFG_2_HND Vector 4 Module 2 2 RETI Vector ...

Page 254: ...with POR Timer_B capture compare control 2 TBCCTL2 Read write 0186h Reset with POR Timer_B capture compare 2 TBCCR2 Read write 0196h Reset with POR Timer_B capture compare control 3 TBCCTL3 Read write 0188h Reset with POR Timer_B capture compare 3 TBCCR3 Read write 0198h Reset with POR Timer_B capture compare control 4 TBCCTL4 Read write 018Ah Reset with POR Timer_B capture compare 4 TBCCR4 Read w...

Page 255: ...4 TBCL5 TBCL6 TBCCR4 CLLDx bits control the update TBCL0 independent 11 TBCL0 TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 TBCL6 TBCCR1 CLLDx bits control the update CNTLx Bits 12 11 Counter Length 00 16 bit TBR max 0FFFFh 01 12 bit TBR max 0FFFh 10 10 bit TBR max 03FFh 11 8 bit TBR max 0FFh Unused Bit 10 Unused TBSSELx Bits 9 8 Timer_B clock source select 00 TBCLK 01 ACLK 10 SMCLK 11 Inverted TBCLK IDx Bits 7 6...

Page 256: ... Bit 1 Timer_B interrupt enable This bit enables the TBIFG interrupt request 0 Interrupt disabled 1 Interrupt enabled TBIFG Bit 0 Timer_B interrupt flag 0 No interrupt pending 1 Interrupt pending TBR Timer_B Register 15 14 13 12 11 10 9 8 TBRx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 TBRx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 TBRx Bits 15 0 Timer_B register The TBR register is the...

Page 257: ...A 01 CCIxB 10 GND 11 VCC SCS Bit 11 Synchronize capture source This bit is used to synchronize the capture input signal with the timer clock 0 Asynchronous capture 1 Synchronous capture CLLDx Bit 10 9 Compare latch load These bits select the compare latch load event 00 TBCLx loads on write to TBCCRx 01 TBCLx loads when TBR counts to 0 10 TBCLx loads when TBR counts to 0 up or continuous mode TBCLx...

Page 258: ...put The selected input signal can be read by this bit OUT Bit 2 Output For output mode 0 this bit directly controls the state of the output 0 Output low 1 Output high COV Bit 1 Capture overflow This bit indicates a capture overflow occurred COV must be reset with software 0 No capture overflow occurred 1 Capture overflow occurred CCIFG Bit 0 Capture compare interrupt flag 0 No interrupt pending 1 ...

Page 259: ...0 Timer_B interrupt vector value TBIV Contents Interrupt Source Interrupt Flag Interrupt Priority 00h No interrupt pending 02h Capture compare 1 TBCCR1 CCIFG Highest 04h Capture compare 2 TBCCR2 CCIFG 06h Capture compare 3 TBCCR3 CCIFG 08h Capture compare 4 TBCCR4 CCIFG 0Ah Capture compare 5 TBCCR5 CCIFG 0Ch Capture compare 6 TBCCR6 CCIFG 0Eh Timer overflow TBIFG Lowest MSP430x14x MSP430x16x devic...

Page 260: ...12 26 Timer_B ...

Page 261: ... chapter discusses the operation of the asynchronous UART mode USART0 is implemented on the MSP430x12xx MSP430x13xx and MSP430x15x devices In addition to USART0 the MSP430x14x and MSP430x16x devices implement a second identical USART module USART1 Topic Page 13 1 USART Introduction UART Mode 13 2 13 2 USART Operation UART Mode 13 4 13 3 USART Registers UART Mode 13 21 Chapter 13 ...

Page 262: ...ndependent transmit and receive shift registers Separate transmit and receive buffer registers LSB first data transmit and receive Built in idle line and address bit communication protocols for multiprocessor systems Receiver start edge detection for auto wake up from LPMx modes Programmable baud rate with modulation for fractional baud rate support Status flags for error detection and suppression...

Page 263: ...olarity Receive Status SYNC CKPH CKPL SSEL1 SSEL0 UCLKI ACLK SMCLK SMCLK 00 01 10 11 OE PE BRK TXWAKE UCLKS UCLKI Receive Control RXERR FE SWRST URXEx URXEIE URXWIE Transmit Control SWRST UTXEx TXEPT RXWAKE SP CHAR PENA PEV SP CHAR PENA PEV WUT UTXD URXD SOMI STE Prescaler Divider UxBRx Modulator UxMCTL Baud Rate Generator UTXIFGx Refer to the device specific datasheet for SFR locations SYNC URXIF...

Page 264: ... chapter USART Module I2C mode for USART0 when reconfiguring from I2C mode to UART mode Note Initializing or Re Configuring the USART Module The required USART initialization re configuration process is 1 Set SWRST BIS B SWRST UxCTL 2 Initialize all USART registers with SWRST 1 including UxCTL 3 Enable USART module via the MEx SFRs URXEx and or UTXEx 4 Clear SWRST via software BIC B SWRST UxCTL 5 ...

Page 265: ...ous ones marks are received after the first stop bit of a character When two stop bits are used for the idle line the second stop bit is counted as the first mark bit of the idle period The first character received after an idle period is an address character The RXWAKE bit is used as an address tag for each block of characters In the idle line multiprocessor format this bit is set when a received...

Page 266: ...flag double buffered with the user accessible TXWAKE bit When the transmitter is loaded from UxTXBUF WUT is also loaded from TXWAKE resetting the TXWAKE bit The following procedure sends out an idle frame to indicate an address character will follow 1 Set TXWAKE then write any character to UxTXBUF UxTXBUF must be ready for new data UTXIFGx 1 The TXWAKE value is shifted to WUT and the contents of U...

Page 267: ...cter to UxRXBUF and set URXIFGx All applicable error status flags are also set If an address is received user software must reset URXWIE to continue receiving data If URXWIE remains set only address characters address bit 1 will be received The URXWIE bit is not modified by the USART hardware automatically Figure 13 4 Address Bit Multiprocessor Format ST Address SP ST Data SP ST Data SP Blocks of ...

Page 268: ...iption Framing error A framing error occurs when a low stop bit is detected When two stop bits are used only the first stop bit is checked for framing error When a framing error is detected the FE bit is set Parity error A parity error is a mismatch between the number of 1s in a character and the value of the parity bit When an address bit is included in the character it is included in the parity ...

Page 269: ...he RX shift register after the character is received Figure 13 5 State Diagram of Receiver Enable Idle State Receiver Enabled Receive Disable Receiver Collects Character URXEx 0 No Valid Start Bit Not Completed URXEx 1 URXEx 0 URXEx 1 Valid Start Bit Handle Interrupt Conditions Character Received URXEx 1 URXEx 0 Note Re Enabling the Receiver Setting URXEx UART Mode When the receiver is disabled UR...

Page 270: ... 0 No Data Written to Transmit Buffer Not Completed UTXEx 1 UTXEx 0 UTXEx 1 Data Written to Transmit Buffer Handle Interrupt Conditions Character Transmitted UTXEx 1 UTXEx 0 And Last Buffer Entry Is Transmitted When the transmitter is enabled UTXEx 1 data should not be written to UxTXBUF unless it is ready for new data indicated by UTXIFGx 1 Violation can result in an erroneous transmission if dat...

Page 271: ...CLK 8 8 UCLKI ACLK SMCLK SMCLK 11 BITCLK 10 01 00 20 27 28 215 Compare 0 or 1 Modulation Data Shift Register LSB first 16 Bit Counter Q0 Q15 m0 m7 8 UxBR1 UxBR0 Toggle FF N R R R UxMCTL 0 or 1 SSEL1 SSEL0 Timing for each bit is shown in Figure 13 8 For each bit received a majority vote is taken to determine the bit value These samples occur at the N 2 1 N 2 and N 2 1 BRCLK periods where N is the n...

Page 272: ...CLK can be adjusted from bit to bit with the modulator to meet timing requirements when a non integer divisor is needed Timing of each bit is expanded by one BRCLK clock cycle if the modulator bit mi is set Each time a bit is received or transmitted the next bit in the modulation control register determines the timing for that bit A set modulation bit increases the division factor by one while a c...

Page 273: ...ce the ideal division factor is 13 65 UxMCTL 6Bh m7 0 m6 1 m5 1 m4 0 m3 1 m2 0 m1 1 and m0 1 The LSB of UxMCTL is used first Start bit Error ǒbaud rate BRCLK 0 1 UxBR 1 1Ǔ 100 2 54 Data bit D0 Error ǒbaud rate BRCLK 1 1 UxBR 2 2Ǔ 100 5 08 Data bit D1 Error ǒbaud rate BRCLK 2 1 UxBR 2 3Ǔ 100 0 29 Data bit D2 Error ǒbaud rate BRCLK 3 1 UxBR 3 4Ǔ 100 2 83 Data bit D3 Error ǒbaud rate BRCLK 4 1 UxBR 3...

Page 274: ...tion Error 0 5x BRCLK Int UxBR 2 m0 Int 13 2 1 6 1 7 Majority Vote Taken Majority Vote Taken UxBR m1 13 1 14 UxBR m2 13 0 13 Majority Vote Taken BRCLK URXDx URXDS tactual Sample URXDS The ideal start bit timing tideal 0 is half the baud rate timing tbaud rate because the bit is tested in the middle of its period The ideal baud rate timing tideal i for the remaining character bits is the baud rate ...

Page 275: ... bit D3 Error ǒbaud rate BRCLK 2x 1 6 4 UxBR 2 1 4Ǔ 100 1 95 Data bit D4 Error ǒbaud rate BRCLK 2x 1 6 5 UxBR 3 1 5Ǔ 100 0 59 Data bit D5 Error ǒbaud rate BRCLK 2x 1 6 6 UxBR 4 1 6Ǔ 100 3 13 Data bit D6 Error ǒbaud rate BRCLK 2x 1 6 7 UxBR 4 1 7Ǔ 100 1 66 Data bit D7 Error ǒbaud rate BRCLK 2x 1 6 8 UxBR 5 1 8Ǔ 100 0 88 Parity bit Error ǒbaud rate BRCLK 2x 1 6 9 UxBR 6 1 9Ǔ 100 3 42 Stop bit 1 Erro...

Page 276: ...r versus the ideal time of the bit period Table 13 2 Commonly Used Baud Rates Baud Rate Data and Errors Divide by A BRCLK 32 768 Hz B BRCLK 1 048 576 Hz Baud Rate A B UxBR1 UxBR0 UxMCTL Max TX Error Max RX Error Synchr RX Error UxBR1 UxBR0 UxMCTL Max TX Error Max RX Error 1200 27 31 873 81 0 1B 03 4 3 4 3 2 03 69 FF 0 0 3 2 2400 13 65 436 91 0 0D 6B 6 3 6 3 4 01 B4 FF 0 0 3 2 4800 6 83 218 45 0 06...

Page 277: ...other character An interrupt request is generated if UTXIEx and GIE are also set UTXIFGx is automatically reset if the interrupt request is serviced or if a character is written to UxTXBUF UTXIFGx is set after a PUC or when SWRST 1 UTXIEx is reset after a PUC or when SWRST 1 The operation is shown is Figure 13 10 Figure 13 10 Transmit Interrupt Operation Clear UTXIEx Clear D Character Moved From B...

Page 278: ...t Operation Clear URXS Clear τ S SYNC Valid Start Bit Receiver Collects Character URXSE From URXD PE FE BRK URXEIE URXWIE RXWAKE Erroneous Character Rejection Non Address Character Rejection Character Received or Break Detected URXIFGx URXIEx Interrupt Service Requested SWRST PUC UxRXBUF Read URXSE IRQA S URXEIE is used to enable or disable erroneous characters from setting URXIFGx When using mult...

Page 279: ... mode or to a low power mode where the source is active If the ISR returns to a low power mode where the BRCLK source is inactive the character will not be received Toggling URXSE clears the URXS signal and re enables the start edge detect feature for future characters See chapter System Resets Interrupts and Operating Modes for information on entering and exiting low power modes The now active BR...

Page 280: ... Suppression USART Receive Not Started URXDx URXS tτ When a glitch is longer than tτ or a valid start bit occurs on URXDx the USART receive operation is started and a majority vote is taken as shown in Figure 13 13 If the majority vote fails to detect a start bit the USART halts character reception If character reception is halted an active BRCLK is not necessary A time out period longer than the ...

Page 281: ...FR interrupt flag register 1 IFG1 Read write 002h 082h with PUC Does not apply to 12xx devices Refer to the register definitions for registers and bit positions for these devices Table 13 4 USART1 Control and Status Registers Register Short Form Register Type Address Initial State USART control register U1CTL Read write 078h 001h with PUC Transmit control register U1TCTL Read write 079h 001h with ...

Page 282: ...rity 1 Even parity SPB Bit 5 Stop bit select Number of stop bits transmitted The receiver always checks for one stop bit 0 One stop bit 1 Two stop bits CHAR Bit 4 Character length Selects 7 bit or 8 bit character length 0 7 bit data 1 8 bit data LISTEN Bit 3 Listen enable The LISTEN bit selects loopback mode 0 Disabled 1 Enabled UTXDx is internally fed back to the receiver SYNC Bit 2 Synchronous m...

Page 283: ...ELx Bits 5 4 Source select These bits select the BRCLK source clock 00 UCLKI 01 ACLK 10 SMCLK 11 SMCLK URXSE Bit 3 UART receive start edge The bit enables the UART receive start edge feature 0 Disabled 1 Enabled TXWAKE Bit 2 Transmitter wake 0 Next character transmitted is data 1 Next character transmitted is an address Unused Bit 1 Unused TXEPT Bit 0 Transmitter empty flag 0 UART is transmitting ...

Page 284: ...condition occurred URXEIE Bit 3 Receive erroneous character interrupt enable 0 Erroneous characters rejected and URXIFGx is not set 1 Erroneous characters received will set URXIFGx URXWIE Bit 2 Receive wake up interrupt enable This bit enables URXIFGx to be set when an address character is received When URXEIE 0 an address character will not set URXIFGx if it is received with errors 0 All received...

Page 285: ...ol Register 1 7 6 5 4 3 2 1 0 215 214 213 212 211 210 29 28 rw rw rw rw rw rw rw rw UxBRx The valid baud rate control range is 3 UxBR 0FFFFh where UxBR UxBR1 UxBR0 Unpredictable receive and transmit timing occurs if UxBR 3 UxMCTL USART Modulation Control Register 7 6 5 4 3 2 1 0 m7 m6 m5 m4 m3 m2 m1 m0 rw rw rw rw rw rw rw rw UxMCTLx Bits 7 0 Modulation bits These bits select the modulation for BR...

Page 286: ...xRXBUF resets the receive error bits the RXWAKE bit and URXIFGx In 7 bit data mode UxRXBUF is LSB justified and the MSB is always reset UxTXBUF USART Transmit Buffer Register 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 rw rw rw rw rw rw rw rw UxTXBUFx Bits 7 0 The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift register and transmitted on UTXDx Wr...

Page 287: ...its ME2 Module Enable Register 2 7 6 5 4 3 2 1 0 UTXE1 URXE1 UTXE0 URXE0 rw 0 rw 0 rw 0 rw 0 Bits 7 6 These bits may be used by other modules See device specific datasheet UTXE1 Bit 5 USART1 transmit enable This bit enables the transmitter for USART1 0 Module not enabled 1 Module enabled URXE1 Bit 4 USART1 receive enable This bit enables the receiver for USART1 0 Module not enabled 1 Module enable...

Page 288: ...rupt Enable Register 2 7 6 5 4 3 2 1 0 UTXIE1 URXIE1 UTXIE0 URXIE0 rw 0 rw 0 rw 0 rw 0 Bits 7 6 These bits may be used by other modules See device specific datasheet UTXIE1 Bit 5 USART1 transmit interrupt enable This bit enables the UTXIFG1 interrupt 0 Interrupt not enabled 1 Interrupt enabled URXIE1 Bit 4 USART1 receive interrupt enable This bit enables the URXIFG1 interrupt 0 Interrupt not enabl...

Page 289: ...modules See device specific datasheet Does not apply to MSP430x12xx devices See IFG2 for the MSP430x12xx USART0 interrupt flag bits IFG2 Interrupt Flag Register 2 7 6 5 4 3 2 1 0 UTXIFG1 URXIFG1 UTXIFG0 URXIFG0 rw 1 rw 0 rw 1 rw 0 Bits 7 6 These bits may be used by other modules See device specific datasheet UTXIFG1 Bit 5 USART1 transmit interrupt flag UTXIFG1 is set when U1TXBUF empty 0 No interr...

Page 290: ...USART0 transmit interrupt flag UTXIFG0 is set when U0TXBUF is empty 0 No interrupt pending 1 Interrupt pending URXIFG0 Bit 0 USART0 receive interrupt flag URXIFG0 is set when U0RXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending MSP430x12xx devices only ...

Page 291: ...13 31 USART Peripheral Interface UART Mode ...

Page 292: ...iscusses the operation of the synchronous peripheral interface or SPI mode USART0 is implemented on the MSP430x12xx MSP430x13xx and MSP430x15x devices In addition to USART0 the MSP430x14x and MSP430x16x devices implement a second identical USART module USART1 Topic Page 14 1 USART Introduction SPI Mode 14 2 14 2 USART Operation SPI Mode 14 4 14 3 USART Registers SPI Mode 14 13 Chapter 14 ...

Page 293: ...n the SYNC bit is set and the I2C bit is cleared SPI mode features include 7 or 8 bit data length 3 pin and 4 pin SPI operation Master or slave modes Independent transmit and receive shift registers Separate transmit and receive buffer registers Selectable UCLK polarity and phase control Programmable UCLK frequency in master mode Independent interrupt capability for receive and transmit Figure 14 ...

Page 294: ...arity Receive Status SYNC CKPH CKPL SSEL1 SSEL0 UCLKI ACLK SMCLK SMCLK 00 01 10 11 OE PE BRK TXWAKE UCLKS UCLKI Receive Control RXERR FE SWRST USPIEx URXEIE URXWIE Transmit Control SWRST USPIEx TXEPT RXWAKE SP CHAR PENA PEV SP CHAR PENA PEV WUT SIMO UTXD URXD SOMI STE Prescaler Divider UxBRx Modulator UxMCTL Baud Rate Generator UTXIFGx Refer to the device specific datasheet for SFR locations SYNC ...

Page 295: ...direction 4 pin slave mode When STE is high RX TX operation of the slave is disabled and SOMI is forced to the input direction When STE is low RX TX operation of the slave is enabled and SOMI operates normally 14 2 1 USART Initialization and Reset The USART is reset by a PUC or by the SWRST bit After a PUC the SWRST bit is automatically set keeping the USART in a reset condition When set the SWRST...

Page 296: ...ge starting with the most significant bit When the character is received the receive data is moved from the RX shift register to the received data buffer UxRXBUF and the receive interrupt flag URXIFGx is set indicating the RX TX operation is complete A set transmit interrupt flag UTXIFGx indicates that data has moved from UxTXBUF to the TX shift register and UxTXBUF is ready for new data It does n...

Page 297: ...to the TX shift register before the start of UCLK is transmitted on SOMI Data on SIMO is shifted into the receive shift register on the opposite edge of UCLK and moved to UxRXBUF when the set number of bits are received When data is moved from the RX shift register to UxRXBUF the URXIFGx interrupt flag is set indicating that data has been received The overrun error bit OE is set when the previousl...

Page 298: ...d the BRCLK source is active Figure 14 4 and Figure 14 5 show the transmit enable state diagrams Figure 14 4 Master Mode Transmit Enable Idle State Transmitter Enabled Transmit Disable Transmission Active USPIEx 0 No Data Written to Transfer Buffer Not Completed USPIEx 1 USPIEx 0 USPIEx 1 Data Written to Transmit Buffer Handle Interrupt Conditions Character Transmitted USPIEx 1 USPIEx 0 And Last B...

Page 299: ...abled Receive Disable Receiver Collects Character USPIEx 0 No Data Written to UxTXBUF Not Completed USPIEx 1 USPIEx 0 USPIEx 1 Handle Interrupt Conditions Character Received USPIEx 1 USPIEx 0 SWRST PUC Data Written to UxTXBUF Figure 14 7 SPI Slave Receive Enable State Diagram Idle State Receive Enabled Receive Disable Receiver Collects Character USPIEx 0 No Clock at UCLK Not Completed USPIEx 1 USP...

Page 300: ...r data transfer Figure 14 8 SPI Baud Rate Generator Bit Start mX BRCLK 8 8 UCLKI ACLK SMCLK SMCLK 11 BITCLK 10 01 00 20 27 28 215 Compare 0 or 1 Modulation Data Shift Register LSB first 16 Bit Counter Q0 Q15 m0 m7 8 UxBR1 UxBR0 Toggle FF N R R R UxMCTL SSEL1 SSEL0 The 16 bit value of UxBR0 UxBR1 is the division factor of the USART clock source BRCLK The maximum baud rate that can be generated in m...

Page 301: ... UCLK are independently configured via the CKPL and CKPH control bits of the USART Timing for each case is shown in Figure 14 9 Figure 14 9 USART SPI Timing CKPH CKPL Cycle UCLK UCLK UCLK UCLK SIMO SOMI SIMO SOMI Move to UxTXBUF RX Sample Points 0 1 0 0 0 1 1 1 0 X 1 X MSB MSB 1 2 3 4 5 6 7 8 LSB LSB TX Data Shifted Out STE ...

Page 302: ...e also set UTXIFGx is automatically reset if the interrupt request is serviced or if a character is written to UxTXBUF UTXIFGx is set after a PUC or when SWRST 1 UTXIEx is reset after a PUC or when SWRST 1 The operation is shown is Figure 14 10 Figure 14 10 Transmit Interrupt Operation Clear UTXIEx Clear D Character Moved From Buffer to Shift Register Interrupt Service Requested SWRST Data moved t...

Page 303: ...nding interrupt is served or when UxRXBUF is read Figure 14 11 Receive Interrupt Operation URXS Clear τ S SYNC Valid Start Bit Receiver Collects Character URXSE From URXD PE FE BRK URXEIE URXWIE RXWAKE Character Received URXIFGx URXIEx Interrupt Service Requested SWRST PUC UxRXBUF Read URXSE IRQA SYNC 1 Clear Figure 14 12 Receive Interrupt State Diagram Receive Character Completed Interrupt Servic...

Page 304: ...register 1 IFG1 Read write 002h 082h with PUC Does not apply to MSP430x12xx devices Refer to the register definitions for registers and bit positions for these devices Table 14 2 USART1 Control and Status Registers Register Short Form Register Type Address Initial State USART control register U1CTL Read write 078h 001h with PUC Transmit control register U1TCTL Read write 079h 001h with PUC Receive...

Page 305: ...1 I2C mode CHAR Bit 4 Character length 0 7 bit data 1 8 bit data LISTEN Bit 3 Listen enable The LISTEN bit selects the loopback mode 0 Disabled 1 Enabled The transmit signal is internally fed back to the receiver SYNC Bit 2 Synchronous mode enable 0 UART mode 1 SPI mode MM Bit 1 Master mode 0 USART is slave 1 USART is master SWRST Bit 0 Software reset enable 0 Disabled USART reset released for ope...

Page 306: ...ling edge of UCLK 1 The inactive level is high data is output with the falling edge of UCLK input data is latched with the rising edge of UCLK SSELx Bits 5 4 Source select These bits select the BRCLK source clock 00 External UCLK valid for slave mode only 01 ACLK valid for master mode only 10 SMCLK valid for master mode only 11 SMCLK valid for master mode only Unused Bit 3 Unused Unused Bit 2 Unus...

Page 307: ...TC 0 FE is unused in slave mode 0 No conflict detected 1 A negative edge occurred on STE indicating bus conflict Undefined Bit 6 Unused OE Bit 5 Overrun error flag This bit is set when a character is transferred into UxRXBUF before the previous character was read OE is automatically reset when UxRXBUF is read when SWRST 1 or can be reset by software 0 No error 1 Overrun error occurred Unused Bit 4...

Page 308: ...ter 1 7 6 5 4 3 2 1 0 215 214 213 212 211 210 29 28 rw rw rw rw rw rw rw rw UxBRx The baud rate generator uses the content of UxBR1 UxBR0 to set the baud rate Unpredictable SPI operation occurs if UxBR 2 UxMCTL USART Modulation Control Register 7 6 5 4 3 2 1 0 m7 m6 m5 m4 m3 m2 m1 m0 rw rw rw rw rw rw rw rw UxMCTLx Bits 7 0 The modulation control register is not used for SPI mode and should be set...

Page 309: ...ading UxRXBUF resets the OE bit and URXIFGx flag In 7 bit data mode UxRXBUF is LSB justified and the MSB is always reset UxTXBUF USART Transmit Buffer Register 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 rw rw rw rw rw rw rw rw UxTXBUFx Bits 7 0 The transmit data buffer is user accessible and contains current data to be transmitted When seven bit character length is used the data should be MSB justifi...

Page 310: ...ic datasheet Does not apply to MSP430x12xx devices See ME2 for the MSP430x12xx USART0 module enable bit ME2 Module Enable Register 2 7 6 5 4 3 2 1 0 USPIE1 USPIE0 rw 0 rw 0 Bits 7 5 These bits may be used by other modules See device specific datasheet USPIE1 Bit 4 USART1 SPI enable This bit enables the SPI mode for USART1 0 Module not enabled 1 Module enabled Bits 3 1 These bits may be used by oth...

Page 311: ...dules See device specific datasheet Does not apply to MSP430x12xx devices See IE2 for the MSP430x12xx USART0 interrupt enable bits IE2 Interrupt Enable Register 2 7 6 5 4 3 2 1 0 UTXIE1 URXIE1 UTXIE0 URXIE0 rw 0 rw 0 rw 0 rw 0 Bits 7 6 These bits may be used by other modules See device specific datasheet UTXIE1 Bit 5 USART1 transmit interrupt enable This bit enables the UTXIFG1 interrupt 0 Interru...

Page 312: ... USART0 transmit interrupt enable This bit enables the UTXIFG0 interrupt 0 Interrupt not enabled 1 Interrupt enabled URXIE0 Bit 0 USART0 receive interrupt enable This bit enables the URXIFG0 interrupt for USART0 0 Interrupt not enabled 1 Interrupt enabled MSP430x12xx devices only ...

Page 313: ...Register 2 7 6 5 4 3 2 1 0 UTXIFG1 URXIFG1 UTXIFG0 URXIFG0 rw 1 rw 0 rw 1 rw 0 Bits 7 6 These bits may be used by other modules See device specific datasheet UTXIFG1 Bit 5 USART1 transmit interrupt flag UTXIFG1 is set when U1TXBUF is empty 0 No interrupt pending 1 Interrupt pending URXIFG1 Bit 4 USART1 receive interrupt flag URXIFG1 is set when U1RXBUF has received a complete character 0 No interr...

Page 314: ...14 23 USART Peripheral Interface SPI Mode ...

Page 315: ...nsmit USART peripheral interface supports I2C communication in USART0 This chapter describes the I2C mode The I2C mode is implemented on the MSP430x15x and MSP430x16x devices Topic Page 15 1 I2C Module Introduction 15 2 15 2 I2C Module Operation 15 4 15 3 I2C Module Registers 15 20 Chapter 15 ...

Page 316: ...ion v2 1 J Byte word format transfer J 7 bit and 10 bit device addressing modes J General call J START RESTART STOP J Multi master transmitter slave receiver mode J Multi master receiver slave transmitter mode J Combined master transmit receive and receive transmit mode J Standard mode up to100 kbps and fast mode up to 400 kbps support Built in FIFO for buffered read and write Programmable clock g...

Page 317: ...ve Shift Register Transmit Shift Register SDA I2C Clock Generator I2CEN SCL MST ACLK SMCLK SMCLK 0 1 00 01 10 11 0 1 LISTEN I2CSSELx 1 No clock I2CIN I2CCLK I2CDRW I2CSCLLOW I2CTXUDF I2CRXOVR I2CSBD I2CWORD I2COA I2CSA I2CPSC I2CSCLL I2CSCLH I2CNDATx I2CRM XA SYNC 1 I2C 1 I2CTRX R W I2CSTB I2CSTP I2CSTT I2CBUSY ...

Page 318: ...the slave when performing data transfers A master initiates a data transfer and gener ates the clock signal SCL Any device addressed by a master is considered a slave I2C data is communicated using the serial data pin SDA and the serial clock pin SCL Both SDA and SCL are bidirectional and must be connected to a positive supply voltage using a pull up resistor Figure 15 2 I2C Bus Connection Diagram...

Page 319: ...egisters are unchanged I2COA I2CSA I2CIE I2CIFG and I2CIV registers are unchanged When re configuring the USART from I2C mode to UART or SPI mode the I2C SYNC and I2CEN bits must first be cleared then the SWRST must be set and the UART or SPI initialization procedure must be followed Failure to follow this procedure could result in unpredictable operation Note Configuring the USART Module for I2C ...

Page 320: ...Data Transfer SDA SCL MSB Acknowledgement Signal From Receiver Acknowledgement Signal From Receiver 1 2 7 8 9 1 2 8 9 ACK ACK START Condition S STOP Condition P R W START and STOP conditions are generated by the master and are shown in Figure 15 3 A START condition is a high to low transition on the SDA line while SCL is high A STOP condition is a low to high transition on the SDA line while SCL i...

Page 321: ...rom the receiver after each byte The next byte is the remaining 8 bits of the 10 bit slave address followed by the ACK bit and the 8 bit data Figure 15 6 I2C Module 10 Bit Addressing Format S 1 Slave Address 1st byte 7 Slave Address 2nd byte ACK R W 1 1 8 ACK 1 Data 8 ACK 1 P 1 1 1 1 1 0 X X Repeated START Conditions The direction of data flow on SDA can be changed by the master without first stop...

Page 322: ...enerated after the I2CNDAT number of bytes have been transferred Software must set I2CSTP to generate a STOP condition at the end of transmission This is used for RESTART conditions 0 1 1 I2CNDAT is used to determine length of transmission Setting I2CSTT initiates activity A STOP condition is automatically generated after I2CNDAT number of bytes have been transferred 1 0 1 I2CNDAT is not used to d...

Page 323: ...e Generate STOP 10 x I2CPSC I2CBB Is Cleared 8 x I2CPSC I2CSTP I2CMST Are Cleared 8 x I2CPSC New START Send I2CDR Low Byte 8 x SCL Send I2CDR High Byte 8 x SCL New START 2 1 2 1 NACKIFG Is Set 3 XA 0 I2CRM 1 I2CRM 0 No No I2CDR Written Ack Ack and I2CWORD 0 Ack No Ack No Ack Yes No Yes I2CSTT 1 I2CDR Empty Yes Yes I2CSTP 1 No 3 Yes No When I2RM 1 I2CSTP must be set before the last I2CDR value is w...

Page 324: ... 10 x I2CPSC I2CBB Is Cleared 8 x I2CPSC 8 x I2CPSC New START Receive Data Low Byte 8 x SCL New START 2 NACKIFG Is Set 2 I2CWORD 0 I2CSTT 1 Generate Ack For Low Byte 1 x SCL Receive Data High Byte 8 x SCL Generate 2nd START 8 x SCL 4 x I2CPSC Ack New START 3 I2CRM 1 I2CRM 0 No No Yes Yes Yes Yes I2CSTP 1 No Yes No IDLE I2CBUSY Is Cleared IDLE I2CBUSY Is Cleared Send Slave Address Bits 9 8 Extended...

Page 325: ...hat lost arbitration switches to the slave receiver mode and sets the arbitration lost flag ALIFG If two or more devices send identical first bytes arbitration continues on the subsequent bytes Figure 15 10 Arbitration Procedure Between Two Master Transmitters 1 0 0 0 1 0 0 0 1 1 1 1 1 n Device 1 Lost Arbitration and Switches Off Bus Line SCL Data From Device 1 Data From Device 2 Bus Line SDA If t...

Page 326: ...d on SDA are shifted in with the clock pulses that are generated by the master device The slave device does not generate the clock but it can hold SCL low if intervention of the CPU is required after a byte has been received In slave receiver mode every byte received will be acknowledged There is no way for a slave to generate a NACK condition for received data Slave transmitter mode is entered wh...

Page 327: ...If Not RESTART 8 x SCL No STOP Detected STTIFG Is Set No Receive Slave Address Bits 9 8 with R W 1 8 x SCL Send Acknowledge 1 x SCL OAIFG Set If Not RESTART I2CDR Loaded I2CBUSY Is Cleared 1 RESTART Detected 1 Yes Yes No Ack No Ack No No I2CDR Empty Yes Yes Ack and I2CWORD 0 4 x I2CPSC 13 x I2CPSC IDLE Receive Slave Address Bits 7 0 8 x SCL Send Acknowledge 1 x SCL Send Acknowledge 1 x SCL XA 0 Ye...

Page 328: ...D 0 Byte Mode STTIFG Is Set I2CBUSY Is Set START Detected I2CBB Is Set 4 x I2CPSC IDLE OAIFG Set If Not RESTART No Yes Yes No Stop State I2CBUSY Is Cleared 1 x I2CPSC 1 From Slave Transmit Mode Send Acknowledge 1 x SCL 8 x SCL Receive Slave Address Bits 9 8 with R W 0 8 x SCL Receive Slave Address Bits 7 0 8 x SCL Send Acknowledge 1 x SCL Send Acknowledge 1 x SCL XA 0 2 Matched I2COA No Match No M...

Page 329: ...w word is written before the previous word has been transmitted the new word is held in a temporary buffer before being latched into the I2CDR register TXRDYIFG is set when I2CDR is ready to be accessed I2CDR should be written after I2CSTT is set 1 0 Word mode receive The low byte of the word was received first then the high byte The register is double buffered If a new word is received before the...

Page 330: ...ble operation can result The I2CSCLL and I2CSCLH registers should be used to set the SCL frequency Figure 15 13 I2C Module SCL Generation I2CCLK I2CIN I2CPSC I2CPSC 2 x I2CSCLH 1 I2CPSC 2 x I2CSCLL 1 During the arbitration procedure the clocks from the different masters must be synchronized A device that first generates a low period on SCL overrules the other devices forcing them to start their ow...

Page 331: ...to idle condition After the I2C module returns to the idle condition control of the clock source reverts to the settings of its control bits Automatic I2C clock activation occurs when In master mode clock activation occurs when I2CSTT 1 and remains active until the transfer completes and the I2C module returns to the idle condition In slave mode clock activation occurs when a START condition is de...

Page 332: ...ter I2CRM 1 All data sent and I2CSTP set Master receiver I2CRM 0 I2CNDAT number of bytes received and all data read from I2CDR Master receiver I2CRM 1 Last byte of data received I2CSTP set and all data read from I2CDR Slave transmitter STOP condition detected Slave receiver STOP condition detected and all data read from I2CDR RXRDYIFG Receive ready interrupt status This flag is set when the I2C mo...

Page 333: ... If another interrupt flag is set another interrupt is immediately generated after servicing the initial interrupt I2CIV Software Example The following software example shows the recommended use of I2CIV The I2CIV value is added to the PC to automatically jump to the appropriate routine I2C_ISR ADD I2CIV PC Add offset to jump table RETI Vector 0 No interrupt JMP ALIFG_ISR Vector 2 ALIFG JMP NACKIF...

Page 334: ...rite 052h Reset with PUC USART control U0CTL Read write 070h 001h with PUC I2C transfer control I2CTCTL Read write 071h Reset with PUC I2C data control I2CDCTL Read only 072h Reset with PUC I2C prescaler I2CPSC Read write 073h Reset with PUC I2C SCL high I2CSCLH Read write 074h Reset with PUC I2C SCL low I2CSCLL Read write 075h Reset with PUC I2C data I2CDRW I2CDRB Read write 076h Reset with PUC I...

Page 335: ...I operation when SYNC 1 0 SPI mode 1 I2C mode XA Bit 4 Extended Addressing 0 7 bit addressing 1 10 bit addressing LISTEN Bit 3 Listen This bit selects loopback mode LISTEN is only valid when MST 1 and I2CTRX 1 master transmitter 0 Normal mode 1 SDA is internally fed back to the receiver loopback SYNC Bit 2 Synchronous mode enable 0 UART mode 1 SPI or I2C mode MST Bit 1 Master This bit selects mast...

Page 336: ...Bit 3 I2C transmit This bit selects the transmit or receive function for the I2C controller when MST 1 When MST 0 the R W bit of the address byte defines the data direction I2CTRX must be reset for proper slave mode operation 0 Receive mode Data is received on the SDA pin 1 Transmit mode Data transmitted on the SDA pin I2CSTB Bit 2 Start byte Setting the I2CSTB bit when MST 1 initiates a start byt...

Page 337: ...ster and is unused in slave mode 0 SCL is not being held low 1 SCL is being held low I2CSBD Bit 3 I2C single byte data This bit indicates if the receive register I2CDRW holds a word or a byte I2CSBD is valid only when I2CWORD 1 0 A complete word was received 1 Only the lower byte in I2CDR is valid I2CTXUDF Bit 2 I2C transmit underflow 0 No underflow occurred 1 Transmit underflow occurred I2CRXOVR ...

Page 338: ...ts 15 8 I2C Data When I2CWORD 1 the register name is I2CDRW When I2CWORD 0 the name is I2CDRB When I2CWORD 1 any attempt to modify the register with a byte instruction will fail and the register will not be updated I2CNDAT I2C Transfer Byte Count Register 7 6 5 4 3 2 1 0 I2CNDATx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 I2CNDATx Bits 7 0 I2C number of bytes This register supports automatic data byt...

Page 339: ... Modifiable only when I2CEN 0 I2CPSCx Bits 7 0 I2C clock prescaler The I2C clock input I2CIN is divided by the I2CPSCx value to produce the internal I2C clock frequency The division rate is I2CPSCx 1 I2CPSCx values 4 are not recommended The I2CSCLL and I2CSCLH registers should be used to set the SCL frequency 000h Divide by 1 001h Divide by 2 0FFh Divide by 256 ...

Page 340: ...002h SCL high period 5 x I2CPSC 1 003h SCL high period 5 x I2CPSC 1 004h SCL high period 6 x I2CPSC 1 0FFh SCL high period 257 x I2CPSC 1 I2CSCLL I2C Shift Clock Low Register 7 6 5 4 3 2 1 0 I2CSCLLx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Modifiable only when I2CEN 0 I2CSCLLx Bits 7 0 I2C shift clock low These bits define the low period of SCL when the I2C controller is in master mode The SCL low...

Page 341: ...ns the local address of the MSP430 I2C controller The I2COA register is right justified Bit 6 is the MSB Bits 15 7 are always 0 I2COA I2C Own Address Register 10 Bit Addressing Mode 15 14 13 12 11 10 9 8 0 0 0 0 0 0 I2COAx r0 r0 r0 r0 r0 r0 rw 0 rw 0 7 6 5 4 3 2 1 0 I2COAx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Modifiable only when I2CEN 0 I2COAx Bits 15 0 I2C own address The I2COA register conta...

Page 342: ...ssed by the MSP430 It is only used in master mode The I2CSA register is right justified Bit 6 is the MSB Bits 15 7 are always 0 I2CSA I2C Slave Address Register 10 Bit Addressing Mode 15 14 13 12 11 10 9 8 0 0 0 0 0 0 I2CSAx r0 r0 r0 r0 r0 r0 rw 0 rw 0 7 6 5 4 3 2 1 0 I2CSAx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 I2CSAx Bits 15 0 I2C slave address The I2CSA register contains the slave address of ...

Page 343: ...When TXDMAEN 1 TXRDYIE is ignored and TXRDYIFG will not generate an interrupt 0 Interrupt disabled 1 Interrupt enabled RXRDYIE Bit 4 Receive ready interrupt enable When RXDMAEN 1 RXRDYIE is ignored and RXRDYIFG will not generate an interrupt 0 Interrupt disabled 1 Interrupt enabled ARDYIE Bit 3 Access ready interrupt enable 0 Interrupt disabled 1 Interrupt enabled OAIE Bit 2 Own address interrupt ...

Page 344: ...rupt pending 1 Interrupt pending TXRDYIFG Bit 5 Transmit ready interrupt flag 0 No interrupt pending 1 Interrupt pending RXRDYIFG Bit 4 Receive ready interrupt flag 0 No interrupt pending 1 Interrupt pending ARDYIFG Bit 3 Access ready interrupt flag 0 No interrupt pending 1 Interrupt pending OAIFG Bit 2 Own address interrupt flag 0 No interrupt pending 1 Interrupt pending NACKIFG Bit 1 No acknowle...

Page 345: ...0 r 0 r 0 r0 I2CIVx Bits 15 0 I2C interrupt vector value I2CIV Contents Interrupt Source Interrupt Flag Interrupt Priority 000h No interrupt pending 002h Arbitration lost ALIFG Highest 004h No acknowledgement NACKIFG 006h Own address OAIFG 008h Register access ready ARDYIFG 00Ah Receive data ready RXRDYIFG 00Ch Transmit data ready TXRDYIFG 00Eh General call GCIFG 010h START condition received STTI...

Page 346: ...15 32 USART Peripheral Interface I2C Mode ...

Page 347: ...is chapter describes Comparator_A Comparator_A is implemented in MSP430x11x1 MSP430x12x MSP430x13x MSP430x14x MSP430x15x and MSP430x16x devices Topic Page 16 1 Comparator_A Introduction 16 2 16 2 Comparator_A Operation 16 4 16 3 Comparator_A Registers 16 9 Chapter 16 ...

Page 348: ...nalog signals Features of Comparator_A include Inverting and non inverting terminal input multiplexer Software selectable RC filter for the comparator output Output provided to Timer_A capture input Software control of the port input buffer Interrupt capability Selectable reference voltage generator Comparator and reference generator can be powered down The Comparator_A block diagram is shown in F...

Page 349: ...Comparator_A Figure 16 1 Comparator_A Block Diagram CAOUT CAEX 0 5x 0 25x Set_CAIFG CA1 CCI1B 0V G D S P2CA0 P2CA1 CAF CARSEL CAON CAREFx 1 0 00 01 10 11 00 01 10 11 1 0 1 0 1 0 1 0 1 0 0V 1 0 VCAREF CA0 0 1 0 1 VCC VCC VCC Tau 2 0ms ...

Page 350: ...ssociated port pins using the P2CAx bits Both comparator terminal inputs can be controlled individually The P2CAx bits allow Application of an external signal to the and terminals of the comparator Routing of an internal reference voltage to an associated output port pin Internally the input switch is constructed as a T switch to suppress distortion in the signal path Note Comparator Input Connect...

Page 351: ...he output filter can reduce errors associated with comparator oscillation Figure 16 2 RC Filter Response at the Output of the Comparator Terminal Terminal Comparator Inputs Comparator Output Unfiltered at CAOUT Comparator Output Filtered at CAOUT 16 2 4 Voltage Reference Generator The voltage reference generator is used to generate VCAREF which can be applied to either comparator input terminal Th...

Page 352: ...s critical any P2 pin connected to analog signals should be disabled with their associated CAPDx bit Figure 16 3 Transfer Characteristic and Power Dissipation in a CMOS Inverter Buffer VCC VSS ICC VO VI 0 VCC VI VCC ICC CAPD x 1 16 2 6 Comparator_A Interrupts One interrupt flag and one interrupt vector are associated with the Comparator_A as shown in Figure 16 4 The interrupt flag CAIFG is set on ...

Page 353: ...s used to calculate the temperature sensed by Rmeas are Two digital I O pins to charge and discharge the capacitor I O set to output high VCC to charge capacitor reset to discharge I O switched to high impedance input with CAPDx set when not in use One output charges and discharges the capacitor via Rref One output discharges capacitor via Rmeas The terminal is connected to the positive terminal o...

Page 354: ... Figure 16 6 Timing for Temperature Measurement Systems VC VCC 0 25 VCC Phase I Charge Phase II Discharge Phase III Charge tref Phase IV Discharge tmeas t Rmeas Rref The VCC voltage and the capacitor value should remain constant during the conversion but are not critical since they cancel in the ratio Nmeas Nref Rmeas C ln Vref VCC Rref C ln Vref VCC Nmeas Nref Rmeas Rref Rmeas Rref Nmeas Nref ...

Page 355: ...d in Table 16 1 Table 16 1 Comparator_A Registers Register Short Form Register Type Address Initial State Comparator_A control register 1 CACTL1 Read write 059h Reset with POR Comparator_A control register 2 CACTL2 Read write 05Ah Reset with POR Comparator_A port disable CAPD Read write 05Bh Reset with POR ...

Page 356: ... 0 VCAREF is applied to the terminal 1 VCAREF is applied to the terminal CAREF Bits 5 4 Comparator_A reference These bits select the reference voltage VCAREF 00 Internal reference off An external reference can be applied 01 0 25 VCC 10 0 50 VCC 11 Diode reference is selected CAON Bit 3 Comparator_A on This bit turns on the comparator When the comparator is off it consumes no current The reference ...

Page 357: ...r_A output is not filtered 1 Comparator_A output is filtered CAOUT Bit 0 Comparator_A output This bit reflects the value of the comparator output Writing this bit has no effect CAPD Comparator_A Port Disable Register 7 6 5 4 3 2 1 0 CAPD7 CAPD6 CAPD5 CAPD4 CAPD3 CAPD2 CAPD1 CAPD0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 CAPDx Bits 7 0 Comparator_A port disable These bits individually disable the in...

Page 358: ...16 12 Comparator_A ...

Page 359: ...it analog to digital converter This chapter describes the ADC12 The ADC12 is implemented in the MSP430x13x MSP430x14x MSP430x15x and MSP430x16x devices Topic Page 17 1 ADC12 Introduction 17 2 17 2 ADC12 Operation 17 4 17 3 ADC12 Registers 17 20 Chapter 17 ...

Page 360: ...by software or timers Conversion initiation by software Timer_A or Timer_B Software selectable on chip reference voltage generation 1 5 V or 2 5 V Software selectable internal or external reference Eight individually configurable external input channels Conversion channels for internal temperature sensor AVCC and external references Independent channel selectable reference sources for both positiv...

Page 361: ...Sample Timer 4 1024 INCHx 4 A0 A1 A2 A3 A4 A5 A6 A7 ADC12MEM0 ADC12MEM15 ADC12MCTL0 ADC12MCTL15 CSTARTADDx 4 4 SHT1x CONSEQx ACLK MCLK SMCLK ADC12SSELx ADC12OSC 00 01 10 11 00 01 10 11 SHSx 00 01 10 11 00 01 10 11 ISSH 1 0 0 1 SREF2 0 1 SREF1 00 01 SREF0 10 ADC12ON BUSY REFON INCHx 0Ah 1 5 V or 2 5 V Reference on Ref_x Ref_x INCHx 0Bh 11 R R 0000 1001 1000 0010 0001 0011 0100 0101 0110 0111 1011 1...

Page 362: ...rol registers ADC12CTL0 and ADC12CTL1 The core is enabled with the ADC12ON bit The ADC12 can be turned off when not in use to save power With few exceptions the ADC12 control bits can only be modified when ENC 0 ENC must be set to 1 before any conversion can take place Conversion Clock Selection The ADC12CLK is used both as the conversion clock and to generate the sampling period when the pulse sa...

Page 363: ...ution method When the inputs are internally switched the switching action may cause transients on the input signal These transients decay and settle before causing errant conversion Figure 17 2 Analog Multiplexer R 100 Ohm ESD Protection ADC12MCTLx 0 3 Input Ax Analog Port Selection The ADC12 inputs are multiplexed with the port P6 pins which are digital CMOS gates When analog signals are applied ...

Page 364: ... to bias the recommended storage capacitors If the internal reference generator is not used for the conversion the storage capacitors are not required Note Reference Decoupling Approximately 200 µA is required from any reference used by the ADC12 while the two LSBs are being resolved during a conversion A parallel combination of 10 µF and 0 1 µF capacitors is recommended for any reference used as ...

Page 365: ...mpling is active The high to low SAMPCON transition starts the analog to digital conversion which requires 13 ADC12CLK cycles Two different sample timing methods are defined by control bit SHP extended sample mode and pulse mode Extended Sample Mode The extended sample mode is selected when SHP 0 The SHI signal directly controls SAMPCON and defines the length of the sample period tsample When SAMP...

Page 366: ...timer keeps SAMPCON high after synchronization with AD12CLK for a programmed interval tsample The total sampling time is tsample plus tsync See Figure 17 4 The SHTx bits select the sampling time in 4x multiples of ADC12CLK SHT0x selects the sampling time for ADC12MCTL0 to 7 and SHT1x selects the sampling time for ADC12MCTL8 to 15 Figure 17 4 Pulse Sample Mode Start Sampling Stop Sampling Conversio...

Page 367: ... for an accurate 12 bit conversion Figure 17 5 Analog Input Equivalent Circuit RS RI VS VC MSP430 CI VI VI Input voltage at pin Ax VS External source voltage RS External source resistance RI Internal MUX on input resistance CI Input capacitance VC Capacitance charging voltage The resistance of the source RS and RI affect tsample The following equation can be used to calculate the minimum sampling ...

Page 368: ...annels or repeat sequence of channels CSTARTADDx points to the first ADC12MCTLx location to be used in a sequence A pointer not visible to software is incremented automatically to the next ADC12MCTLx in a sequence when each conversion completes The sequence continues until an EOS bit in ADC12MCTLx is processed this is the last control byte processed When conversion results are written to a selecte...

Page 369: ...iggered by the ADC12SC bit When any other trigger source is used ENC must be toggled between each conversion Figure 17 6 Single Channel Single Conversion Mode ADC12 off x CSTARTADDx Wait for Enable ENC Wait for Trigger Sample Input Channel Defined in ADC12MCTLx ENC ENC SHSx 0 and ENC 1 or and ADC12SC SAMPCON SAMPCON 1 Convert SAMPCON ENC 0 ENC 0 12 x ADC12CLK Conversion Completed Result Stored Int...

Page 370: ...ces can be triggered by the ADC12SC bit When any other trigger source is used ENC must be toggled between each sequence Figure 17 7 Sequence of Channels Mode ADC12 off x CSTARTADDx Wait for Enable ENC Wait for Trigger Sample Input Channel Defined in ADC12MCTLx ENC ENC SHSx 0 and ENC 1 or and ADC12SC SAMPCON SAMPCON 1 Convert SAMPCON 12 x ADC12CLK Conversion Completed Result Stored Into ADC12MEMx A...

Page 371: ...d is overwritten by the next conversion Figure 17 8 shows repeat single channel mode Figure 17 8 Repeat Single Channel Mode ADC12 off x CSTARTADDx Wait for Enable ENC Wait for Trigger Sample Input Channel Defined in ADC12MCTLx ENC ENC SHSx 0 and ENC 1 or and ADC12SC SAMPCON SAMPCON 1 Convert SAMPCON 12 x ADC12CLK Conversion Completed Result Stored Into ADC12MEMx ADC12IFG x is Set 1 x ADC12CLK ADC1...

Page 372: ...ce of channels mode Figure 17 9 Repeat Sequence of Channels Mode ADC12 off x CSTARTADDx Wait for Enable ENC Wait for Trigger Sample Input Channel Defined in ADC12MCTLx ENC ENC SHSx 0 and ENC 1 or and ADC12SC SAMPCON SAMPCON 1 SAMPCON 12 x ADC12CLK Conversion Completed Result Stored Into ADC12MEMx ADC12IFG x is Set 1 x ADC12CLK ADC12ON 1 CONSEQx 11 MSC 1 and SHP 1 and ENC 1 or EOS x 0 ENC 0 and EOS...

Page 373: ...t Stopping Conversions Stopping ADC12 activity depends on the mode of operation The recommended ways to stop an active conversion or conversion sequence are Resetting ENC in single channel single conversion mode stops a conversion immediately and the results are unpredictable For correct results poll the busy bit until reset before clearing ENC Resetting ENC during repeat single channel operation ...

Page 374: ...r than 30 µs The temperature sensor offset error can be large and may need to be calibrated for most applications See device specific datasheet for parameters Selecting the temperature sensor automatically turns on the on chip reference generator as a voltage source for the temperature sensor However it does not enable the VREF output or affect the reference selections for the conversion The refer...

Page 375: ...converter The connections shown in Figure 17 11 help avoid this In addition to grounding ripple and noise spikes on the power supply lines due to digital switching or switching power supplies can corrupt the conversion result A noise free design using separate analog and digital ground planes with a single point connection is recommend to achieve high accuracy Figure 17 11 ADC12 Grounding and Nois...

Page 376: ...rupt The highest priority enabled ADC12 interrupt generates a number in the ADC12IV register see register description This number can be evaluated or added to the program counter to automatically enter the appropriate software routine Disabled ADC12 interrupts do not affect the ADC12IV value Any access read or write of the ADC12IV register automatically resets the ADC12OV condition or the ADC12TOV...

Page 377: ...check immediately if a higher prioritized interrupt occurred during the processing of ADC12IFG15 This saves nine cycles if another ADC12 interrupt is pending Interrupt handler for ADC12 INT_ADC12 Enter Interrupt Service Routine 6 ADD ADC12IV PC Add offset to PC 3 RETI Vector 0 No interrupt 5 JMP ADOV Vector 2 ADC overflow 2 JMP ADTOV Vector 4 ADC timing overflow 2 JMP ADM0 Vector 6 ADC12IFG0 2 Vec...

Page 378: ... ADC12MEM11 Read write 0156h Unchanged ADC12 memory 12 ADC12MEM12 Read write 0158h Unchanged ADC12 memory 13 ADC12MEM13 Read write 015Ah Unchanged ADC12 memory 14 ADC12MEM14 Read write 015Ch Unchanged ADC12 memory 15 ADC12MEM15 Read write 015Eh Unchanged ADC12 memory control 0 ADC12MCTL0 Read write 080h Reset with POR ADC12 memory control 1 ADC12MCTL1 Read write 081h Reset with POR ADC12 memory co...

Page 379: ... when ENC 0 SHT1x Bits 15 12 Sample and hold time These bits define the number of ADC12CLK cycles in the sampling period for registers ADC12MEM8 to ADC12MEM15 SHT0x Bits 11 8 Sample and hold time These bits define the number of ADC12CLK cycles in the sampling period for registers ADC12MEM0 to ADC12MEM7 SHTx Bits ADC12CLK cycles 0000 4 0001 8 0010 16 0011 32 0100 64 0101 96 0110 128 0111 192 1000 2...

Page 380: ... Reference on ADC12ON Bit 4 ADC12 on 0 ADC12 off 1 ADC12 on ADC12OVIE Bit 3 ADC12MEMx overflow interrupt enable The GIE bit must also be set to enable the interrupt 0 Overflow interrupt disabled 1 Overflow interrupt enabled ADC12 TOVIE Bit 2 ADC12 conversion time overflow interrupt enable The GIE bit must also be set to enable the interrupt 0 Conversion time overflow interrupt disabled 1 Conversio...

Page 381: ...RTADDx is 0 to 0Fh corresponding to ADC12MEM0 to ADC12MEM15 SHSx Bits 11 10 Sample and hold source select 00 ADC12SC bit 01 Timer_A OUT1 10 Timer_B OUT0 11 Timer_B OUT1 SHP Bit 9 Sample and hold pulse mode select This bit selects the source of the sampling signal SAMPCON to be either the output of the sampling timer or the sample input signal directly 0 SAMPCON signal is sourced from the sample in...

Page 382: ...2 busy This bit indicates an active sample or conversion operation 0 No operation is active 1 A sequence sample or conversion is active ADC12MEMx ADC12 Conversion Memory Registers 15 14 13 12 11 10 9 8 0 0 0 0 Conversion Results r0 r0 r0 r0 rw rw rw rw 7 6 5 4 3 2 1 0 Conversion Results rw rw rw rw rw rw rw rw Conversion Results Bits 15 0 The 12 bit conversion results are right justified Bit 11 is...

Page 383: ...e SREFx Bits 6 4 Select reference 000 VR AVCC and VR AVSS 001 VR VREF and VR AVSS 010 VR VeREF and VR AVSS 011 VR VeREF and VR AVSS 100 VR AVCC and VR VREF VeREF 101 VR VREF and VR VREF VeREF 110 VR VeREF and VR VREF VeREF 111 VR VeREF and VR VREF VeREF INCHx Bits 3 0 Input channel select 0000 A0 0001 A1 0010 A2 0011 A3 0100 A4 0101 A5 0110 A6 0111 A7 1000 VeREF 1001 VREF VeREF 1010 Temperature se...

Page 384: ...Interrupt disabled 1 Interrupt enabled ADC12IFG ADC12 Interrupt Flag Register 15 14 13 12 11 10 9 8 ADC12 IFG15 ADC12 IFG14 ADC12 IFG13 ADC12 IFG12 ADC12 IFG11 ADC12 IFG10 ADC12 IFG9 ADC12 IFG8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 ADC12 IFG7 ADC12 IFG6 ADC12 IFG5 ADC12 IFG4 ADC12 IFG3 ADC12 IFG2 ADC12 IFG1 ADC12 IFG0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12IFGx Bits 15 0 AD...

Page 385: ...DC12IFG0 008h ADC12MEM1 interrupt flag ADC12IFG1 00Ah ADC12MEM2 interrupt flag ADC12IFG2 00Ch ADC12MEM3 interrupt flag ADC12IFG3 00Eh ADC12MEM4 interrupt flag ADC12IFG4 010h ADC12MEM5 interrupt flag ADC12IFG5 012h ADC12MEM6 interrupt flag ADC12IFG6 014h ADC12MEM7 interrupt flag ADC12IFG7 016h ADC12MEM8 interrupt flag ADC12IFG8 018h ADC12MEM9 interrupt flag ADC12IFG9 01Ah ADC12MEM10 interrupt flag ...

Page 386: ...17 28 ADC12 ...

Page 387: ...ormance 10 bit analog to digital converter This chapter describes the ADC10 The ADC10 is implemented in the MSP430x11x2 MSP430x12x2 devices Topic Page 18 1 ADC10 Introduction 18 2 18 2 ADC10 Operation 18 4 18 3 ADC10 Registers 18 24 Chapter 18 ...

Page 388: ...n rate Monotonic10 bit converter with no missing codes Sample and hold with programmable sample periods Conversion initiation by software or Timer_A Software selectable on chip reference voltage generation 1 5 V or 2 5 V Software selectable internal or external reference Eight external input channels Conversion channels for internal temperature sensor VCC and external references Selectable convers...

Page 389: ...REFBURST ADC10SSELx ADC10DIVx SHSx ADC10SHTx MSC ENC BUSY ADC10DF ADC10CLK SREF2 ADC10TB ADC10B1 ADC10CT ISSH ADC10SR ADC10OSC Ref_x S H Convert SAMPCON 1 0 Sync Sample Timer 4 8 16 64 SHI ADC10SA n 4 A0 A1 A2 A3 A4 A5 A6 A7 REFON INCHx 0Ah 1 5 V or 2 5 V Reference on Ref_x SREF1 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 11 0 1 SREF0 1011 REFOUT 1010 10 CONSEQx 1 0 INCHx 0Bh Auto ADC10...

Page 390: ...ult when using straight binary format is NADC 1023 Vin VR VR VR The ADC10 core is configured by two control registers ADC10CTL0 and ADC10CTL1 The core is enabled with the ADC10ON bit With few exceptions the ADC10 control bits can only be modified when ENC 0 ENC must be set to 1 before any conversion can take place Conversion Clock Selection The ADC10CLK is used both as the conversion clock and to ...

Page 391: ...itching action may cause transients on the input signal These transients decay and settle before causing errant conversion Figure 18 2 Analog Multiplexer R 100Ohm ESD Protection INCHx Input Ax Analog Port Selection The ADC10 external inputs A0 to A4 and VeREF and VREF share terminals with I O port P2 which are digital CMOS gates Optional inputs A5 to A7 are shared on port P3 on selected devices se...

Page 392: ...en REFON 0 both are disabled The total settling time when REFON becomes set is 30 µs When REFON 1 but no conversion is active the buffer is automatically disabled and automatically re enabled when needed When the buffer is disabled it consumes no current In this case the band gap voltage source remains enabled When REFOUT 1 the REFBURST bit controls the operation of the internal reference buffer W...

Page 393: ...al source can be inverted with the ISSH bit The SHTx bits select the sample period tsample to be 4 8 16 or 64 ADC10CLK cycles The sampling timer sets SAMPCON high for the selected sample period after synchronization with ADC10CLK Total sampling time is tsample plus tsync The high to low SAMPCON transition starts the analog to digital conversion which requires 13 ADC10CLK cycles as shown in Figure ...

Page 394: ... RI VS VC MSP430 CI VI VI Input voltage at pin Ax VS External source voltage RS External source resistance RI Internal MUX on input resistance CI Input capacitance VC Capacitance charging voltage The resistance of the source RS and RI affect tsample The following equations can be used to calculate the minimum sampling time tsample for a 10 bit conversion When ADC10SR 0 t sample u RS RI ln 211 CI 8...

Page 395: ... 1 Table 18 1 Conversion Mode Summary CONSEQx Mode Operation 00 Single channel single conversion A single channel is converted once 01 Sequence of channels A sequence of channels is converted once 10 Repeat single channel A single channel is converted repeatedly 11 Repeat sequence of channels A sequence of channels is converted repeatedly ...

Page 396: ...ns can be triggered by the ADC10SC bit When any other trigger source is used ENC must be toggled between each conversion Figure 18 5 Single Channel Single Conversion Mode ADC10 Off x INCHx Wait for Enable ENC Wait for Trigger Sample Input Channel ENC ENC SHS 0 and ENC 1 or and ADC10SC SAMPCON Convert ENC 0 ENC 0 12 x ADC10CLK Conversion Completed Result to ADC10MEM ADC10IFG is Set 1 x ADC10CLK Con...

Page 397: ... triggers a sequence successive sequences can be triggered by the ADC10SC bit When any other trigger source is used ENC must be toggled between each sequence Figure 18 6 Sequence of Channels Mode ADC10 Off x INCHx Wait for Enable ENC Wait for Trigger Sample Input Channel Ax ENC ENC SHS 0 and ENC 1 or and ADC10SC SAMPCON Convert 12 x ADC10CLK Conversion Completed Result to ADC10MEM ADC10IFG is Set ...

Page 398: ...s the repeat single channel mode Figure 18 7 Repeat Single Channel Mode ADC10 Off x INCHx Wait for Enable ENC Wait for Trigger ENC ENC SHS 0 and ENC 1 or and ADC10SC SAMPCON 4 8 16 64 ADC10CLK Convert 12 x ADC10CLK Conversion Completed Result to ADC10MEM ADC10IFG is Set 1 x ADC10CLK ADC10ON 1 CONSEQx 10 MSC 1 and ENC 1 ENC 0 MSC 0 and ENC 1 Sample Input Channel Ax x input channel Ax ...

Page 399: ... re starts the sequence Figure 18 8 shows the repeat sequence of channels mode Figure 18 8 Repeat Sequence of Channels Mode ADC10 Off x INCHx Wait for Enable ENC Wait for Trigger Sample Input Channel Ax ENC ENC SHS 0 and ENC 1 or and ADC10SC Convert 12 x ADC10CLK Conversion Completed Result to ADC10MEM ADC10IFG is Set 1 x ADC10CLK ADC10ON 1 CONSEQx 11 MSC 1 and ENC 1 or x 0 ENC 0 and x 0 MSC 0 and...

Page 400: ...quence modes The function of the ENC bit is unchanged when using the MSC bit Stopping Conversions Stopping ADC10 activity depends on the mode of operation The recommended ways to stop an active conversion or conversion sequence are Resetting ENC in single channel single conversion mode stops a conversion immediately and the results are unpredictable For correct results poll the ADC10BUSY bit until...

Page 401: ...triggered No software intervention is required to manage the ADC10 until the predefined amount of conversion data has been transferred Each DTC transfer requires one CPU MCLK To avoid any bus contention during the DTC transfer the CPU is halted if active for the one MCLK required for the transfer A DTC transfer must not be initiated while the ADC10 is busy Software must ensure that no active conve...

Page 402: ...s pointer is initially equal to ADC10SA and the internal transfer counter is initially equal to n The internal pointer and counter are not visible to software The DTC transfers the word value of ADC10MEM to the address pointer ADC10SA After each DTC transfer the internal address pointer is incremented by two and the internal transfer counter is decremented by one The DTC transfers continue with ea...

Page 403: ...DC10MEM is written Wait for CPU ready Write to ADC10MEM completed Transfer data to Address AD AD AD 2 x x 1 Synchronize with MCLK 1 x MCLK cycle n is latched in counter x x 0 DTC init Wait for write to ADC10SA Write to ADC10SA Write to ADC10SA x 0 Prepare DTC DTC operation Write to ADC10SA or n 0 Write to ADC10SA x n AD SA n 0 ADC10IFG 1 ADC10TB 0 and ADC10CT 0 ADC10TB 0 and ADC10CT 1 n 0 ...

Page 404: ...pointer and counter are not visible to software The DTC transfers the word value of ADC10MEM to the address pointer ADC10SA After each DTC transfer the internal address pointer is incremented by two and the internal transfer counter is decremented by one The DTC transfers continue with each loading of ADC10MEM until the internal transfer counter becomes equal to zero At this point block one is ful...

Page 405: ...M is written Wait for CPU ready Write to ADC10MEM completed Transfer data to Address AD AD AD 2 x x 1 Synchronize with MCLK 1 x MCLK cycle n is latched in counter x x 0 DTC init Wait for write to ADC10SA Write to ADC10SA Write to ADC10SA x 0 Prepare DTC DTC operation Write to ADC10SA or n 0 ADC10IFG 1 Toggle ADC10B1 Write to ADC10SA x n If ADC10B1 0 then AD SA ADC10B1 1 or ADC10CT 1 ADC10CT 0 and ...

Page 406: ...e time is dependent on the MSP430 operating mode and clock system setup If the MCLK source is active but the CPU is off the DTC uses the MCLK source for each transfer without re enabling the CPU If the MCLK source is off the DTC temporarily restarts MCLK sourced with DCOCLK only during a transfer The CPU remains off and after the DTC transfer MCLK is again turned off The maximum DTC cycle time for...

Page 407: ...an 30 µs The temperature sensor offset error can be large and may need to be calibrated for most applications See the device specific datasheet for the parameters Selecting the temperature sensor automatically turns on the on chip reference generator as a voltage source for the temperature sensor However it does not enable the VREF output or affect the reference selections for the conversion The r...

Page 408: ...f care is not taken this current can generate small unwanted offset voltages that can add to or subtract from the reference or input voltages of the A D converter The connections shown in Figure 18 15 help avoid this In addition to grounding ripple and noise spikes on the power supply lines due to digital switching or switching power supplies can corrupt the conversion result A noise free design i...

Page 409: ...s used ADC10DTC1 0 ADC10IFG is set when a block transfer completes and the internal transfer counter n 0 If both the ADC10IE and the GIE bits are set then the ADC10IFG flag generates an interrupt request The ADC10IFG flag is automatically reset when the interrupt request is serviced or may be reset by software Figure 18 17 ADC10 Interrupt System D Q IRQ Interrupt Service Requested Reset ADC10CLK P...

Page 410: ...Ah Reset with POR ADC10 control register 0 ADC10CTL0 Read write 01B0h Reset with POR ADC10 control register 1 ADC10CTL1 Read write 01B2h Reset with POR ADC10 memory ADC10MEM Read 01B4h Unchanged ADC10 data transfer control register 0 ADC10DTC0 Read write 048h Reset with POR ADC10 data transfer control register 1 ADC10DTC1 Read write 049h Reset with POR ADC10 data transfer start address ADC10SA Rea...

Page 411: ...VeREF 110 VR VeREF and VR VREF VeREF 111 VR VeREF and VR VREF VeREF ADC10 SHTx Bits 12 11 ADC10 sample and hold time 00 4 x ADC10CLKs 01 8 x ADC10CLKs 10 16 x ADC10CLKs 11 64 x ADC10CLKs ADC10SR Bit 10 ADC10 sampling rate This bit selects the reference buffer drive capability for the maximum sampling rate Setting ADC10SR reduces the current consumption of the reference buffer 0 Reference buffer su...

Page 412: ...n ADC10ON Bit 4 ADC10 on 0 ADC10 off 1 ADC10 on ADC10IE Bit 3 ADC10 interrupt enable 0 Interrupt disabled 1 interrupt enabled ADC10IFG Bit 2 ADC10 interrupt flag This bit is set if ADC10MEM is loaded with a conversion result It is automatically reset when the interrupt request is accepted or it may be reset by software When using the DTC this flag is set when a block of transfers is completed 0 No...

Page 413: ...e conversion or the highest channel for a sequence of conversions 0000 A0 0001 A1 0010 A2 0011 A3 0100 A4 0101 A5 0110 A6 0111 A7 1000 VeREF 1001 VREF VeREF 1010 Temperature sensor 1011 VCC VSS 2 1100 VCC VSS 2 1101 VCC VSS 2 1110 VCC VSS 2 1111 VCC VSS 2 SHSx Bits 11 10 Sample and hold source select 00 ADC10SC bit 01 Timer_A OUT1 10 Timer_A OUT0 11 Timer_A OUT2 ADC10DF Bit 9 ADC10 data format 0 S...

Page 414: ...equence of channels 10 Repeat single channel 11 Repeat sequence of channels ADC10 BUSY Bit 0 ADC10 busy This bit indicates an active sample or conversion operation 0 No operation is active 1 A sequence sample or conversion is active ADC10AE Analog Input Enable Control Register 7 6 5 4 3 2 1 0 ADC10AE7 ADC10AE6 ADC10AE5 ADC10AE4 ADC10AE3 ADC10AE2 ADC10AE1 ADC10AE0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0...

Page 415: ...he 10 bit conversion results are right justified straight binary format Bit 9 is the MSB Bits 15 10 are always 0 ADC10MEM Conversion Memory Register 2 s Complement Format 15 14 13 12 11 10 9 8 Conversion Results r r r r r r r r 7 6 5 4 3 2 1 0 Conversion Results 0 0 0 0 0 0 r r r0 r0 r0 r0 r0 r0 Conversion Results Bits 15 0 The 10 bit conversion results are left justified 2 s complement format Bit...

Page 416: ...sfer 0 Data transfer stops when one block one block mode or two blocks two block mode have completed 1 Data is transferred continuously DTC operation is stopped only if ADC10CT cleared or ADC10SA is written to ADC10B1 Bit 1 ADC10 block one This bit indicates for two block mode which block is filled with ADC10 conversion results ADC10B1 is valid only after ADC10IFG has been set the first time durin...

Page 417: ... DTC is disabled 01h 0FFh Number of transfers per block ADC10SA Start Address Register for Data Transfer 15 14 13 12 11 10 9 8 ADC10SAx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 1 rw 0 7 6 5 4 3 2 1 0 ADC10SAx 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r0 ADC10SAx Bits 15 1 ADC10 start address These bits are the start address for the DTC A write to register ADC10SA is required to initiate DTC transfers Unused Bi...

Page 418: ...18 32 ADC10 ...

Page 419: ...e output digital to analog converter This chapter describes the DAC12 Two DAC12 modules are implemented in the MSP430x15x and MSP430x16x devices Topic Page 19 1 DAC12 Introduction 19 2 19 2 DAC12 Operation 19 4 19 3 DAC12 Registers 19 10 Chapter 19 ...

Page 420: ...ht binary or 2 s compliment data format Self calibration option for offset correction Synchronized update capability for multiple DAC12s Note Multiple DAC12 Modules Some devices may integrate more than one DAC12 module In the case where more than one DAC12 is present on a device the multiple DAC12 modules operate identically Throughout this chapter nomenclature appears such as DAC12_xDAT or DAC12_...

Page 421: ...12_1DAT DAC12_1Latch TB2 TA1 DAC12DF DAC12RES AVSS 00 01 10 11 00 01 10 11 00 01 10 11 VeREF VREF DAC12DF DAC12RES Latch Bypass DAC12LSELx TB2 TA1 00 01 10 11 00 01 10 11 Latch Bypass DAC12IR To ADC12 module DAC12_1DAT Updated DAC12_0DAT Updated 1 0 0 1 ENC 0 1 ENC DAC12GRP 1 0 DAC12GRP DAC12SREFx AVSS 00 01 10 11 x3 3 DAC12_1OUT DAC12AMPx 3 x3 DAC12IR 3 Group Load Logic DAC12AMPx 3 ...

Page 422: ... data format the formula for the output voltage is given in Table 19 1 Table 19 1 DAC12 Full Scale Range Vref VeREF or VREF Resolution DAC12RES DAC12IR Output Voltage Formula 12 bit 0 0 Vout Vref 3 DAC12_xDAT 4096 12 bit 0 1 Vout Vref DAC12_xDAT 4096 8 bit 1 0 Vout Vref 3 DAC12_xDAT 256 8 bit 1 1 Vout Vref DAC12_xDAT 256 In 8 bit mode the maximum useable value for DAC12_xDAT is 0FFh and in 12 bit ...

Page 423: ...w low setting the settling time is the slowest and the current consumption of both buffers is the lowest The medium and high settings have faster settling times but the current consumption increases See the device specific data sheet for parameters 19 2 3 Updating the DAC12 Voltage Output The DAC12_xDAT register can be connected directly to the DAC12 core or double buffered The trigger for updatin...

Page 424: ...2 Bit Straight Binary Mode Full Scale Output 0 0FFFh 0 Output Voltage DAC Data When using 2 s compliment data format the range is shifted such that a DAC12_xDAT value of 0800h 0080h in 8 bit mode results in a zero output voltage 0000h is the mid scale output voltage and 07FFh 007Fh for 8 bit mode is the full scale voltage output as shown in Figure 19 3 Figure 19 3 Output Voltage vs DAC12 Data 12 B...

Page 425: ... the output amplifier has a positive offset a digital input of zero does not result in a zero output voltage The DAC12 output voltage reaches the maximum output level before the DAC12 data reaches the maximum code This is shown in Figure 19 5 Figure 19 5 Positive Offset Vcc Output Voltage 0 DAC Data Full Scale Code The DAC12 has the capability to calibrate the offset voltage of the output amplifie...

Page 426: ...ouped both DAC12_xDAT registers must be written to before the outputs update even if data for one or both of the DACs is not changed Figure 19 6 shows a latch update timing example for grouped DAC12_0 and DAC12_1 When DAC12_0 DAC12GRP 1 and both DAC12_x DAC12LSELx 0 and either DAC12ENC 0 neither DAC12 will update Figure 19 6 DAC12 Group Update Example Timer_A3 Trigger DAC12_0 DAC12GRP DAC12_0 DAC1...

Page 427: ...terrupt The DAC12IFG bit is set when DAC12LSELx 0 and DAC12 data is latched from the DAC12_xDAT register into the data latch When DAC12LSELx 0 the DAC12IFG flag is not set A set DAC12IFG bit indicates that the DAC12 is ready for new data If both the DAC12IE and GIE bits are set the DAC12IFG generates an interrupt request The DAC12IFG flag is not reset automatically It must be reset by software ...

Page 428: ... 2 DAC12 Registers Register Short Form Register Type Address Initial State DAC12_0 control DAC12_0CTL Read write 01C0h Reset with POR DAC12_0 data DAC12_0DAT Read write 01C8h Reset with POR DAC12_1 control DAC12_1CTL Read write 01C2h Reset with POR DAC12_1 data DAC12_1DAT Read write 01CAh Reset with POR ...

Page 429: ... load trigger for the DAC12 latch DAC12ENC must be set for the DAC to update except when DAC12LSELx 0 00 DAC12 latch loads when DAC12_xDAT written DAC12ENC is ignored 01 DAC12 latch loads when DAC12_xDAT written or when grouped when all DAC12_xDAT registers in the group have been written 10 Rising edge of Timer_A OUT1 TA1 11 Rising edge of Timer_B OUT2 TB2 DAC12 CALON Bit 9 DAC12 calibration on Th...

Page 430: ...m speed current 110 Medium speed current High speed current 111 High speed current High speed current DAC12DF Bit 4 DAC12 data format 0 Straight binary 1 2 s compliment DAC12IE Bit 3 DAC12 interrupt enable 0 Disabled 1 Enabled DAC12IFG Bit 2 DAC12 Interrupt flag 0 No interrupt pending 1 Interrupt pending DAC12 ENC Bit 1 DAC12 enable conversion This bit enables the DAC12 module when DAC12LSELx 0 wh...

Page 431: ...AC12 core DAC12 Data Bits 11 0 DAC12 data DAC12 Data Format DAC12 Data 12 bit binary The DAC12 data are right justified Bit 11 is the MSB 12 bit 2 s complement The DAC12 data are right justified Bit 11 is the MSB sign 8 bit binary The DAC12 data are right justified Bit 7 is the MSB Bits 11 8 are don t care and do not effect the DAC12 core 8 bit 2 s complement The DAC12 data are right justified Bit...

Page 432: ...19 14 DAC12 ...

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