Texas Instruments MSP430F6723, Manual

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NOTE: This only affects debug mode.'
LCDB5
LCDB Module
Category
Functional
Function Static DC charge can built up on dedicated COMx pins.
Description If the device is set into LPMx.5, its dedicated COMx pins (not shared with GPIO function)
are floating. External leakage paths to these pins can result in dedicated COMx pins being
charged. This can lead to static DC voltages being applied to the external LCD display.
This might cause long term over-stress to the LCD display and/or cause certain LCD
segments to flare up when device wakes up from LPMx.5 mode.
Workaround Connect a high-resistance resistor between the dedicated COM pins and Vss to
permanently discharge the affected pins.
LCDB6
LCDB Module
Category
Functional
Function LCD outputs may be corrupted by modifying register fields VLCDx and/or LCDCPEN of
LCDCVCTL register while LCDON (LCDCCTL0) is set
Description Writing to VLCDx and/or LCDCPEN register bits in LCDCVCTL register while LCDC
is enabled (LCDON = '1' in LCDCCTL0 register) may corrupt the LCD output due to
incorrect start-up of LCD-controller and internal voltage generation.
Workaround Do not modify VLCDx and/or LCDCPEN bits in LCDCVCTL register while LCDON = '1'
PMM7
PMM Module
Category
Functional
Function PMMRIE default conditions different than user guide
Description The user guide specifies that, after a BOR reset condition, the SVS will not be configured
to trigger a POR signal in the condition that the monitored voltages fall below the SVS
level(s). This is not true for this device. The SVS Low and SVS High Side POR Enable
bits (SVSLPE/SVSHPE) in the Power Management System Reset Enable and Interrupt
Enable register are set by default (PMMRIE = 0x1100).
Workaround If this behavior is not desired, reset the SVSLPE/SVSHPE bits in the PMMRIE register at
the beggining of the application.
PMM11
PMM Module
Category
Functional
Function MCLK comes up fast on exit from LPM3 and LPM4
Description The DCO exceeds the programmed frequency of operation on exit from LPM3 and
LPM4 for up to 6 us. This behavior is masked from affecting code execution by default:
SVSL and SVML run in normal-performance mode and mask CPU execution for 150
us on wakeup from LPM3 and LPM4. However ,when the low-side SVS and the SVM
are disabled or are operating in full-performance mode (SVMLE= 0 and SVSLE= 0, or
SVMLFP= 1 and SVSLFP= 1) AND MCLK is sourced from the internal DCO running over
Advisory Descriptions www.ti.com
16 MSP430F6723 Microcontroller SLAZ340AF – OCTOBER 2012 – REVISED MAY 2021
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