Workaround
- Use XT2 as the SMCLK oscillator source instead of the DCO
or
- Do not disable the clock request bit for SMCLKREQEN in the Unified Clock System
Control 8 Register (UCSCTL8). This means that all modules that depend on SMCLK to
operate successfully should be halted or disabled before entering LPM3 or LPM4. If the
increased frequency prevents the proper function of an affected module, wait 32, 48, 80
or 100 cycles for core voltage levels 0, 1, 2, or 3, respectively, before re-enabling the
module. (for example, __delay_cycles(100)
PMM14
PMM Module
Category
Functional
Function
Increasing the core level when SVS/SVM low side is configured in full-performance mode
causes device reset
Description
When the SVS/SVM low side is configured in full performance mode
(SVSMLCTL.SVSLFP = 1), the setting time delay for the SVS comparators is ~2us. When
increasing the core level in full-performance mode; the core voltage does not settle to the
new level before the settling time delay of the SVS/SVM comparator expires. This results
in a device reset.
Workaround
When increasing the core level; enable the SVS/SVM low side in normal mode
(SVSMLCTL.SVSLFP=0). This provides a settling time delay of approximately 150us
allowing the core sufficient time to increase to the expected voltage before the delay
expires.
PMM15
PMM Module
Category
Functional
Function
Device may not wake up from LPM2, LPM3, or LPM4
Description
Device may not wake up from LPM2, LPM3 or LMP4 if an interrupt occurs within 1
us after the entry to the specified LPMx; entry can be caused either by user code or
automatically (for example, after a previous ISR is completed). Device can be recovered
with an external reset or a power cycle. Additionally, a PUC can also be used to reset
the failing condition and bring the device back to normal operation (for example, a PUC
caused by the WDT).
This effect is seen when:
- A write to the SVSMHCTL and SVSMLCTL registers is immediately followed
by an LPM2, LPM3, LPM4 entry without waiting the requisite settling time
((PMMIFG.SVSMLDLYIFG = 0 and PMMIFG.SVSMHDLYIFG = 0)).
or
The following two conditions are met:
- The SVSL module is configured for a fast wake-up or when the SVSL/SVML module is
turned off. The affected SVSMLCTL register settings are shaded in the following table.
Advisory Descriptions
SLAZ657S – FEBRUARY 2015 – REVISED MAY 2021
MSP430F6720A Microcontroller
17
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