Function
LCD outputs may be corrupted by modifying register fields VLCDx and/or LCDCPEN of
LCDCVCTL register while LCDON (LCDCCTL0) is set
Description
Writing to VLCDx and/or LCDCPEN register bits in LCDCVCTL register while LCDC
is enabled (LCDON = '1' in LCDCCTL0 register) may corrupt the LCD output due to
incorrect start-up of LCD-controller and internal voltage generation.
Workaround
Do not modify VLCDx and/or LCDCPEN bits in LCDCVCTL register while LCDON = '1'
PMM7
PMM Module
Category
Functional
Function
PMMRIE default conditions different than user guide
Description
The user guide specifies that, after a BOR reset condition, the SVS will not be configured
to trigger a POR signal in the condition that the monitored voltages fall below the SVS
level(s). This is not true for this device. The SVS Low and SVS High Side POR Enable
bits (SVSLPE/SVSHPE) in the Power Management System Reset Enable and Interrupt
Enable register are set by default (PMMRIE = 0x1100).
Workaround
If this behavior is not desired, reset the SVSLPE/SVSHPE bits in the PMMRIE register at
the beggining of the application.
PMM11
PMM Module
Category
Functional
Function
MCLK comes up fast on exit from LPM3 and LPM4
Description
The DCO exceeds the programmed frequency of operation on exit from LPM3 and
LPM4 for up to 6 us. This behavior is masked from affecting code execution by default:
SVSL and SVML run in normal-performance mode and mask CPU execution for 150
us on wakeup from LPM3 and LPM4. However ,when the low-side SVS and the SVM
are disabled or are operating in full-performance mode (SVMLE= 0 and SVSLE= 0, or
SVMLFP= 1 and SVSLFP= 1) AND MCLK is sourced from the internal DCO running over
4 MHz, 7 MHz,11 MHz,or 14 MHz at core voltage levels 0, 1, 2, and 3, respectively, the
mask lasts only 2 us. MCLK is, therefore, susceptible to run out of spec for 4 us.
Workaround
Set the MCLK divide bits in the Unified Clock System Control 5 Register (UCSCTL5) to
divide MCLK by two prior to entering LPM3 or LPM4 (set DIVMx= 001). This prevents
MCLK from running out of spec when the CPU wakes from the low-power mode.
Following the wakeup fromthe low-power mode, wait 32, 48, 80, or 100 cycles for core
voltage levels 0, 1, 2, and 3, respectively, before resetting DIVM xto zero and running
MCLK at full speed [for example, __delay_cycles(100)]
PMM12
PMM Module
Category
Functional
Function
SMCLK comesup fast on exit from LPM3 and LPM4
Description
The DCO exceeds the programmed frequency of operationon exit from LPM3 and LPM4
for up to 6 us. When SMCLK is sourced by the DCO, it is not masked on exit from LPM3
or LPM4. Therefore, SMCLK exceeds the programmed frequency of operation on exit
from LPM3 and LPM4 for up to 6 us. The increased frequency has the potential to change
the expected timing behavior of peripherals that select SMCLK as the clock source.
Advisory Descriptions
16
MSP430F6720A Microcontroller
SLAZ657S – FEBRUARY 2015 – REVISED MAY 2021
Copyright © 2021 Texas Instruments Incorporated
