Texas Instruments MSP430F643 Series Manual Download Page 8

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100

P6.4/CB4/A4

P6.5/CB5/A5

P6.6/CB6/A6

P6.7/CB7/A7

P7.4/CB8/A12

P7.5/CB9/A13

P7.6/CB10/A14

P7.7/CB11/A15

P5.0/VREF+/VeREF+

P5.1/VREF−/VeREF−

AVCC1

AVSS1

XIN

XOUT

DVCC1

DVSS1

VCORE

P5.2/R23

LCDCAP/R33

COM0

P5.3/COM1/S42

P9.7/S0

P9.6/S1

P9.5/S2

P9.4/S3

P9.3/S4

P9.2/S5

P9.1/S6

P9.0/S7

P8.7/S8

P8.6/UCB1SOMI/UCB1SCL/S9

P8.5/UCB1SIMO/UCB1SDA/S10

DVCC2

DVSS2

P2.0/P2MAP0

P6.3/CB3/A3

P6.2/CB2/A2

P6.1/CB1/A1

P6.0/CB0/A0

RST/NMI/SBWTDIO

PJ.3/TCK

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

TEST/SBWTCK

P7.3/XT2OUT

P7.2/XT2IN

LDOI

LDOO

PU.1

PU.0

VSSU

VSS3

P1.3/T

A0.2/S36

P1.4/T

A0.3/S35

AVSS2

P5.6/ADC12CLK/DMAE0

P5.4/COM2/S41

P5.5/COM3/S40

P1.0/T

A0CLK/ACLK/S39

P3.0/T

A1CLK/CBOUT/S31

P3.1/T

A1.0/S30

P3.2/T

A1.1/S29

P1.6/T

A0.1/S33

P1.7/T

A0.2/S32

P1.1/T

A0.0/S38

P1.2/T

A0.1/S37

P1.5/T

A0.4/S34

P3.3/T

A1.2/S28

P3.4/T

A2CLK/SMCLK/S27

P3.5/T

A2.0/S26

P3.6/T

A2.1/S25

P3.7/T

A2.2/S24

P4.0/TB0.0/S23

P4.2/TB0.2/S21

P4.1/TB0.1/S22

P4.4/TB0.4/S19

P4.3/TB0.3/S20

P4.6/TB0.6/S17

P4.5/TB0.5/S18

P8.0/TB0CLK/S15

P4.7/TB0OUTH/SVMOUT/S16

P8.4

/S11

/UCB1CLK/UCA1STE

VBAK

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

P2.6/P2MAP6/R03

P2.7/P2MAP7/LCDREF/R13

DVCC3

DVSS3

VBA

P5.7/R

TCCLK

P8.1/UCB1STE/UCA1CLK/S14

P8.2/UCA1TXD/UCA1SIMO/S13

P8.3/UCA1RXD/UCA1SOMI/S12

MSP430F6435
MSP430F6433

PZ PACKAGE

(TOP VIEW)

MSP430F6438, MSP430F6436, MSP430F6435, MSP430F6433

SLAS720D – AUGUST 2010 – REVISED DECEMBER 2015

www.ti.com

4.2

Pin Designation – MSP430F6435IPZ, MSP430F6433IPZ

Figure 4-2

shows the pinout for the MSP430F6435 and MSP430F6433 devices in the PZ package.

CAUTION: LCDCAP/R33 must be connected to DV

if not used.

Figure 4-2. 100-Pin PZ Package (Top View) – MSP430F6435, MSP430F6433

Terminal Configuration and Functions

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Product Folder Links:

MSP430F6438 MSP430F6436 MSP430F6435 MSP430F6433

Summary of Contents for MSP430F643 Series

Page 1: ...e up From Standby Mode in 3 s Typical Dual 12 Bit Digital to Analog Converters DACs 16 Bit RISC Architecture Extended Memory up to With Synchronization 20 MHz System Clock Voltage Comparator Flexible...

Page 2: ...to active mode in 3 s typical The MSP430F643x devices are microcontrollers with an integrated 3 3 V LDO a high performance 12 bit ADC a comparator two USCIs a hardware multiplier DMA four 16 bit timer...

Page 3: ...T2IN XT2OUT Power Management LDO SVM SVS Brownout SYS Watchdog P2 Port Mapping Controller I O Ports P3 P4 2 8 I Os Interrupt Capability PB 1 16 I Os I O Ports P5 P6 2 8 I Os PC 1 16 I Os I O Ports P7...

Page 4: ...DAC Dynamic Specifications 49 VCC Excluding External Current 20 5 50 12 Bit DAC Dynamic Specifications Continued 50 5 7 Thermal Resistance Characteristics 21 5 51 Comparator_B 51 5 8 Schmitt Trigger I...

Page 5: ...the Test Conditions for the Channel to channel crosstalk parameter 50 Changed the value of DAC12_xDAT from 7F7h to F7Fh and changed the x axis label from fToggle to 1 fToggle in Figure 5 22 Crosstalk...

Page 6: ...ta symbolization and PCB design guidelines are available at www ti com packaging 3 Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare regi...

Page 7: ...ACLK S39 P3 0 TA1CLK CBOUT S31 P3 1 TA1 0 S30 P3 2 TA1 1 S29 P1 6 TA0 1 S33 P1 7 TA0 2 S32 P1 1 TA0 0 S38 P1 2 TA0 1 S37 P1 5 TA0 4 S34 P3 3 TA1 2 S28 P3 4 TA2CLK SMCLK S27 P3 5 TA2 0 S26 P3 6 TA2 1 S...

Page 8: ...1 TA1 0 S30 P3 2 TA1 1 S29 P1 6 TA0 1 S33 P1 7 TA0 2 S32 P1 1 TA0 0 S38 P1 2 TA0 1 S37 P1 5 TA0 4 S34 P3 3 TA1 2 S28 P3 4 TA2CLK SMCLK S27 P3 5 TA2 0 S26 P3 6 TA2 1 S25 P3 7 TA2 2 S24 P4 0 TB0 0 S23 P...

Page 9: ...436 MSP430F6435 MSP430F6433 www ti com SLAS720D AUGUST 2010 REVISED DECEMBER 2015 4 3 Pin Designation MSP430F6438IZQW MSP430F6436IZQW MSP430F6435IZQW MSP430F6433IZQW Figure 4 3 shows the pin diagram f...

Page 10: ...input CB9 Analog input A13 ADC General purpose digital I O Comparator_B input CB10 P7 6 CB10 A14 DAC0 7 D2 I O Analog input A14 ADC DAC12 0 output not available on F6435 and F6433 devices General purp...

Page 11: ...h port interrupt and mappable secondary function P2 6 P2MAP6 R03 23 K2 I O Default mapping no secondary function Input output port of lowest analog LCD voltage V5 General purpose digital I O with port...

Page 12: ...with port interrupt P1 5 TA0 4 S34 39 L6 I O Timer TA0 CCR4 capture CCI4A input compare Out4 output LCD segment output S34 General purpose digital I O with port interrupt P1 6 TA0 1 S33 40 J7 I O Time...

Page 13: ...1 output LCD segment output S22 General purpose digital I O with port interrupt P4 2 TB0 2 S21 52 L10 I O Timer TB0 capture CCR2 CCI2A CCI2B input compare Out2 output LCD segment output S21 General pu...

Page 14: ...out USCI_B1 I2 C data LCD segment output S10 General purpose digital I O P8 6 UCB1SOMI UCB1SCL S9 66 G9 I O USCI_B1 SPI slave out master in USCI_B1 I2 C clock LCD segment output S9 General purpose dig...

Page 15: ...ut DVCC3 89 A6 Digital power supply DVSS3 90 A5 Digital ground supply Test mode pin selects digital I O on JTAG pins TEST SBWTCK 91 B6 I Spy Bi Wire input clock General purpose digital I O PJ 0 TDO 92...

Page 16: ...General purpose digital I O P6 3 CB3 A3 100 D5 I O Comparator_B input CB3 Analog input A3 ADC E5 E6 E8 F4 F5 Reserved N A F8 Reserved TI recommends connecting to ground DVSS AVSS G5 G8 H5 H8 H9 16 Ter...

Page 17: ...at 500 V HBM allows safe manufacturing with a standard ESD control process Pins listed as 1000 V may actually have higher performance 2 JEDEC document JEP157 states that 250 V CDM allows safe manufact...

Page 18: ...ncy maximum MCLK frequency 4 5 2 V VCC 3 6 V fSYSTEM MHz see Figure 5 1 PMMCOREVx 2 0 16 0 2 2 V VCC 3 6 V PMMCOREVx 3 0 20 0 2 4 V VCC 3 6 V 4 The MSP430 CPU is clocked directly with MCLK Both the hi...

Page 19: ...r mode 2 5 4 A 3 V 3 6 6 7 0 11 10 12 18 0 1 6 1 8 2 4 4 7 6 5 10 5 2 2 V 1 1 6 1 9 4 8 6 6 2 1 7 2 0 4 9 6 7 Low power mode 3 ILPM3 XT1LF 0 1 9 2 1 2 7 5 0 6 8 10 8 A crystal mode 6 4 1 1 9 2 1 5 1 7...

Page 20: ...tive no current drawn on VBAK 12 Internal regulator disabled No data retention CPUOFF 1 SCG0 1 SCG1 1 OSCOFF 1 PMMREGOFF 1 LPM4 5 fDCO fACLK fMCLK fSMCLK 0 MHz 5 6 Low Power Mode With LCD Supply Curre...

Page 21: ...g LCD2B 0 1 3 bias LCDCPEN 1 charge pump enabled VLCDx 1000 VLCD 3 V typical LCDSSEL 0 LCDPREx 101 LCDDIVx 00011 fLCD 32768 Hz 32 4 256 Hz Even segments S0 S2 0 odd segments S1 S3 1 No LCD panel load...

Page 22: ...ration t int is met It may be set by trigger signals shorter than t int 5 10 Leakage Current General Purpose I O over recommended ranges of supply voltage and operating free air temperature unless oth...

Page 23: ...to hold the maximum voltage drop specified 5 13 Output Frequency Ports P1 P2 and P3 over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST C...

Page 24: ...Level Output Voltage V OL I Typical Low Level Output Current mA OL MSP430F6438 MSP430F6436 MSP430F6435 MSP430F6433 SLAS720D AUGUST 2010 REVISED DECEMBER 2015 www ti com 5 14 Typical Characteristics Ou...

Page 25: ...V P3 2 CC V Low Level Output Voltage V OL I Typical Low Level Output Current mA OL MSP430F6438 MSP430F6436 MSP430F6435 MSP430F6433 www ti com SLAS720D AUGUST 2010 REVISED DECEMBER 2015 5 15 Typical C...

Page 26: ...s XIN and XOUT Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins If confor...

Page 27: ...MHz 40 50 60 fFault HF Oscillator fault frequency 7 XT2BYPASS 1 8 30 300 kHz 1 Requires external capacitors at both terminals Values are specified by crystal manufacturers 2 To improve EMI on the XT2...

Page 28: ...FO over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT REFO oscillator current IREFO TA 25 C 1 8 V to 3 6...

Page 29: ...z fDCO 4 0 DCO frequency 4 0 DCORSELx 4 DCOx 0 MODx 0 1 3 3 2 MHz fDCO 4 31 DCO frequency 4 31 DCORSELx 4 DCOx 31 MODx 0 12 3 28 2 MHz fDCO 5 0 DCO frequency 5 0 DCORSELx 5 DCOx 0 MODx 0 2 5 6 0 MHz f...

Page 30: ...IT Core voltage active VCORE3 AM 2 4 V DVCC 3 6 V 0 mA I VCORE 21 mA 1 90 V mode PMMCOREV 3 Core voltage active VCORE2 AM 2 2 V DVCC 3 6 V 0 mA I VCORE 21 mA 1 80 V mode PMMCOREV 2 Core voltage active...

Page 31: ...wer Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User s Guide SLAU208 on recommended settings and usage 5 24 PMM SVM High Side over recommended range...

Page 32: ...SVSLFP 1 4 MHz Wake up time from LPM2 PMMCOREV SVSMLRRL n tWAKE UP SLOW LPM3 or LPM4 to active where n 0 1 2 or 3 150 165 s mode 2 SVSLFP 0 Wake up time from LPM3 5 or tWAKE UP LPM5 2 3 ms LPM4 5 to a...

Page 33: ...nless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT TA 40 C 0 43 VBAT 1 7 V TA 25 C 0 52 DVCC not connected TA 60 C 0 58 RTC running TA 85 C 0 64 TA 40 C 0 50 VBAT 2 2 V TA 25 C 0 59...

Page 34: ...put data setup time ns 2 4 V 30 PMMCOREV 3 3 V 25 1 8 V 0 PMMCOREV 0 3 V 0 tHD MI SOMI input data hold time ns 2 4 V 0 PMMCOREV 3 3 V 0 UCLK edge to SIMO valid 1 8 V 20 CL 20 pF 3 V 18 PMMCOREV 0 tVAL...

Page 35: ...HI 1 fUCxCLK MSP430F6438 MSP430F6436 MSP430F6435 MSP430F6433 www ti com SLAS720D AUGUST 2010 REVISED DECEMBER 2015 Figure 5 11 SPI Master Mode CKPH 0 Figure 5 12 SPI Master Mode CKPH 1 Copyright 2010...

Page 36: ...3 V 5 tHD SI SIMO input data hold time ns 2 4 V 5 PMMCOREV 3 3 V 5 UCLK edge to SOMI valid 1 8 V 76 CL 20 pF 3 V 60 PMMCOREV 0 tVALID SO SOMI output data valid time 2 ns UCLK edge to SOMI valid 2 4 V...

Page 37: ...fUCxCLK tLO HI tLO HI tSTE LAG tSTE DIS tSTE ACC tHD SO MSP430F6438 MSP430F6436 MSP430F6435 MSP430F6433 www ti com SLAS720D AUGUST 2010 REVISED DECEMBER 2015 Figure 5 13 SPI Slave Mode CKPH 0 Figure 5...

Page 38: ...0 10 fSCL SCL clock frequency 2 2 V 3 V 0 400 kHz fSCL 100 kHz 4 0 tHD STA Hold time repeated START 2 2 V 3 V s fSCL 100 kHz 0 6 fSCL 100 kHz 4 7 tSU STA Setup time for a repeated START 2 2 V 3 V s fS...

Page 39: ...T 1 2 4 3 6 V pump disabled Capacitor on LCDCAP when charge LCDCPEN 1 VLCDx 0000 CLCDCAP 4 7 4 7 10 F pump enabled charge pump enabled fLCD 2 mux fFRAME fFrame LCD frame frequency range 0 100 Hz mux 1...

Page 40: ...DCPEN 1 VLCDx 1010 2 V to 3 6 V 3 17 LCDCPEN 1 VLCDx 1011 2 V to 3 6 V 3 24 LCDCPEN 1 VLCDx 1100 2 V to 3 6 V 3 30 LCDCPEN 1 VLCDx 1101 2 2 V to 3 6 V 3 36 LCDCPEN 1 VLCDx 1110 2 2 V to 3 6 V 3 42 LCD...

Page 41: ...MAX UNIT For specified performance of ADC12 linearity parameters using an external reference voltage or 0 45 4 8 5 0 AVCC as reference 1 fADC12CLK ADC conversion clock For specified performance of ADC...

Page 42: ...LSB EG Gain error 3 See 2 2 2 V 3 V 2 4 LSB ET Total unadjusted error See 2 2 2 V 3 V 2 5 LSB 1 Parameters are derived using the histogram method 2 AVCC as reference voltage is selected by SREF2 0 SRE...

Page 43: ...elected 4 Error of conversion result 1 LSB 1 The temperature sensor is provided by the REF module See the REF module parametric IREF regarding the current consumption of the temperature sensor 2 The t...

Page 44: ...e input capacitance Ci is also the dynamic load for an external reference during conversion The dynamic impedance of the reference supply should follow the recommendations on analog source impedance t...

Page 45: ...EFOUT 0 75 REFON 0 1 Settling time of reference tSETTLE s AVCC AVCC min through AVCC max voltage 8 CVREF CVREF max 75 REFVSEL 0 1 2 REFOUT 1 REFON 0 1 1 The reference is supplied to the ADC by the REF...

Page 46: ...recommended ranges of supply voltage and operating free air temperature unless otherwise noted see Figure 5 17 PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Resolution 12 bit monotonic 12 bits VeREF...

Page 47: ...G dT 2 2 V 3 V 10 coefficient 1 FSR C DAC12AMPx 2 165 Time for offset tOffset_Cal DAC12AMPx 3 5 2 2 V 3 V 66 ms calibration 4 DAC12AMPx 4 6 7 16 5 4 The offset calibration can be done if DAC12AMPx 2 3...

Page 48: ...AT 0h DAC12IR 1 0 0 1 DAC12AMPx 7 RLoad 3 k VeREF AVCC AVCC DAC12_xDAT 0FFFh DAC12IR 1 AVCC 0 13 DAC12AMPx 7 Maximum DAC12 CL DAC12 2 2 V 3 V 100 pF load capacitance DAC12AMPx 2 DAC12_xDAT 0FFFh 1 VO...

Page 49: ...e 48 k for each channel when divide is enabled Can be increased if performance can be maintained 6 When DAC12IR 1 and DAC12SREFx 0 or 1 for both channels the reference input resistive dividers for eac...

Page 50: ...P MAX UNIT DAC12AMPx 2 3 4 DAC12SREFx 2 40 DAC12IR 1 DAC12_xDAT 800h 3 dB bandwidth VDC 1 5 V DAC12AMPx 5 6 DAC12SREFx 2 BW 3dB 2 2 V 3 V 180 kHz VAC 0 1 VPP DAC12IR 1 DAC12_xDAT 800h see Figure 5 21...

Page 51: ...RMD 01 10 10 CIN Input capacitance 5 pF ON switch closed 3 4 k RSIN Series input resistance OFF switch open 50 M CBPWRMD 00 CBF 0 450 ns Propagation delay tPD CBPWRMD 01 CBF 0 600 response time CBPWRM...

Page 52: ...operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS MIN MAX UNIT VLDOO 3 3 V 10 IOH 25 mA VOH High level output voltage 2 4 V See Figure 5 24 for typical characteristics V...

Page 53: ...H LDO input detection threshold 3 75 V VLDOI LDO input voltage Normal operation 3 76 5 5 V VLDO LDO output voltage 3 3 9 V LDOO terminal input voltage with LDO VLDO_EXT LDO disabled 1 8 3 6 V disabled...

Page 54: ...MHz FCTL4 MRG0 1 or FCTL4 MRG1 1 1 The cumulative program time must not be exceeded when writing to a 128 byte flash block This parameter applies to all programming methods individual word or byte wr...

Page 55: ...pins 6 2 CPU The MSP430 CPU has a 16 bit RISC architecture that is highly transparent to the application All operations other than program flow instructions are performed as register operations in co...

Page 56: ...ion ADD R4 R5 R4 R5 R5 Single operands destination only CALL R8 PC TOS R8 PC Relative jump un conditional JNE Jump on equal bit 0 Table 6 2 Address Mode Descriptions ADDRESS MODE S 1 D 1 SYNTAX EXAMPL...

Page 57: ...LPM2 CPU is disabled MCLK FLL loop control and DCOCLK are disabled DC generator of the DCO remains enabled ACLK remains active Low power mode 3 LPM3 CPU is disabled MCLK FLL loop control and DCOCLK ar...

Page 58: ...Ah 53 TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4 Timer TA0 Maskable 0FFE8h 52 TA0IFG TA0IV 1 3 LDO PWR LDOOFFIG LDOONIFG LDOOVLIFG Maskable 0FFE6h 51 DMA0IFG DMA1IFG DMA2IFG DMA3IFG DMA Maskable 0FFE4h 50 DMA4I...

Page 59: ...tor 2 N A 4KB 4KB 0053FFh 004400h 0053FFh 004400h RAM Sector 1 4KB 4KB 4KB 0043FFh 003400h 0043FFh 003400h 0043FFh 003400h Sector 0 4KB 4KB 4KB 0033FFh 002400h 0033FFh 002400h 0033FFh 002400h Sector 7...

Page 60: ...device programmers Table 6 6 lists the JTAG pin requirements For further details on interfacing to development tools and device programmers see the MSP430 Hardware Tools User s Guide SLAU278 For a com...

Page 61: ...le byte single word and long word writes to the flash memory Features of the flash memory include Flash memory has n segments of main memory and four segments of information memory A to D of 128 bytes...

Page 62: ...ombination of input output and interrupt conditions is possible Programmable pullup or pulldown on all ports Programmable drive strength on all ports Edge selectable interrupt input capability for all...

Page 63: ...VSS Disables the output driver and the input Schmitt trigger to prevent parasitic cross currents 31 0FFh 1 PM_ANALOG when applying analog signals 1 The value of the PM_ANALOG mnemonic is set to 0FFh T...

Page 64: ...the proper internal reset signal to the device during power on and power off The SVS and SVM circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltag...

Page 65: ...o interrupt pending 00h Brownout BOR 02h Highest RST NMI BOR 04h PMMSWBOR BOR 06h LPM3 5 or LPM4 5 wakeup BOR 08h Security violation BOR 0Ah SVSL POR 0Ch SVSH POR 0Eh SVML_OVP POR 10h SYSRSTIV System...

Page 66: ...NEL TRIGGER 0 1 2 3 4 5 0 DMAREQ 1 TA0CCR0 CCIFG 2 TA0CCR2 CCIFG 3 TA1CCR0 CCIFG 4 TA1CCR2 CCIFG 5 TA2CCR0 CCIFG 6 TA2CCR2 CCIFG 7 TBCCR0 CCIFG 8 TBCCR2 CCIFG 9 Reserved 10 Reserved 11 Reserved 12 Res...

Page 67: ...timing TA0 also has extensive interrupt capabilities Interrupts may be generated from the counter on overflow conditions and from each capture compare register Table 6 12 Timer TA0 Signal Connections...

Page 68: ...LE DEVICE OUTPUT PIN NUMBER MODULE INPUT INPUT OUTPUT OUTPUT BLOCK PZ ZQW PZ ZQW SIGNAL SIGNAL SIGNAL SIGNAL 42 P3 0 L7 P3 0 TA1CLK TACLK ACLK ACLK Timer NA NA SMCLK SMCLK 42 P3 0 L7 P3 0 TA1CLK TACLK...

Page 69: ...tions INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER MODULE INPUT INPUT OUTPUT OUTPUT BLOCK PZ ZQW PZ ZQW SIGNAL SIGNAL SIGNAL SIGNAL 46 P3 4 J8 P3 4 TA2CLK TACLK ACLK ACLK Timer NA NA...

Page 70: ...Sx 2 DVCC VCC 51 P4 1 M11 P4 1 TB0 1 CCI1A 51 P4 1 M11 P4 1 P2MAPx 1 P2MAPx 1 TB0 1 CCI1B P2MAPx 1 P2MAPx 1 CCR1 TB1 TB0 1 ADC12 internal DVSS GND ADC12SHSx 3 DVCC VCC 52 P4 2 L10 P4 2 TB0 2 CCI2A 52...

Page 71: ...LCD The LCD_B controller has dedicated data memories to hold segment drive information Common and segment signals are generated as defined by the mode Static 2 mux 3 mux and 4 mux LCDs are supported T...

Page 72: ...6 34 0380h 000h 02Eh Timer TB0 see Table 6 35 03C0h 000h 02Eh Timer TA2 see Table 6 36 0400h 000h 02Eh Battery Backup see Table 6 37 0480h 000h 01Fh RTC_B see Table 6 38 04A0h 000h 01Fh 32 bit Hardwa...

Page 73: ...Flash control 3 FCTL3 04h Flash control 4 FCTL4 06h Table 6 20 CRC16 Registers Base Address 0150h REGISTER DESCRIPTION REGISTER OFFSET CRC data input CRC16DI 00h CRC result CRC16INIRES 04h Table 6 21...

Page 74: ...REGISTER OFFSET Port mapping password PMAPPWD 00h Port mapping control PMAPCTL 02h Port P2 0 mapping P2MAP0 00h Port P2 1 mapping P2MAP1 01h Port P2 2 mapping P2MAP2 02h Port P2 3 mapping P2MAP3 03h...

Page 75: ...E 1Ah Port P3 interrupt flag P3IFG 1Ch Port P4 input P4IN 01h Port P4 output P4OUT 03h Port P4 direction P4DIR 05h Port P4 pullup pulldown enable P4REN 07h Port P4 drive strength P4DS 09h Port P4 sele...

Page 76: ...DS 08h Port P9 selection P9SEL 0Ah Table 6 32 Port J Registers Base Address 0320h REGISTER DESCRIPTION REGISTER OFFSET Port PJ input PJIN 00h Port PJ output PJOUT 02h Port PJ direction PJDIR 04h Port...

Page 77: ...ompare control 4 TB0CCTL4 0Ah Capture compare control 5 TB0CCTL5 0Ch Capture compare control 6 TB0CCTL6 0Eh TB0 counter TB0R 10h Capture compare 0 TB0CCR0 12h Capture compare 1 TB0CCR1 14h Capture com...

Page 78: ...h RTC days RTCDAY 14h RTC month RTCMON 15h RTC year low RTCYEARL 16h RTC year high RTCYEARH 17h RTC alarm minutes RTCAMIN 18h RTC alarm hours RTCAHOUR 19h RTC alarm day of week RTCADOW 1Ah RTC alarm d...

Page 79: ...ol DMA module control 4 DMACTL4 08h DMA general control DMA interrupt vector DMAIV 0Ah DMA channel 0 control DMA0CTL 00h DMA channel 0 source address low DMA0SAL 02h DMA channel 0 source address high...

Page 80: ...rol 1 UCA0CTL1 01h USCI baud rate 0 UCA0BR0 06h USCI baud rate 1 UCA0BR1 07h USCI modulation control UCA0MCTL 08h USCI status UCA0STAT 0Ah USCI receive buffer UCA0RXBUF 0Ch USCI transmit buffer UCA0TX...

Page 81: ...UCB1BR1 07h USCI synchronous status UCB1STAT 0Ah USCI synchronous receive buffer UCB1RXBUF 0Ch USCI synchronous transmit buffer UCB1TXBUF 0Eh USCI I2C own address UCB1I2COA 10h USCI I2C slave address...

Page 82: ...13 ADC12MEM13 3Ah Conversion memory 14 ADC12MEM14 3Ch Conversion memory 15 ADC12MEM15 3Eh Table 6 46 DAC12_A Registers Base Address 0780h REGISTER DESCRIPTION REGISTER OFFSET DAC12_A channel 0 control...

Page 83: ...control LCDBBLKCTL 004h LCD_B memory control LCDBMEMCTL 006h LCD_B voltage control LCDBVCTL 008h LCD_B port control 0 LCDBPCTL0 00Ah LCD_B port control 1 LCDBPCTL1 00Ch LCD_B port control 2 LCDBPCTL2...

Page 84: ...VCC P1REN x Pad Logic 1 P1DS x 0 Low drive 1 High drive D Bus Keeper S32 S39 LCDS32 LCDS39 MSP430F6438 MSP430F6436 MSP430F6435 MSP430F6433 SLAS720D AUGUST 2010 REVISED DECEMBER 2015 www ti com 6 13 In...

Page 85: ...1 3 TA0 2 S36 3 P1 3 I O I 0 O 1 0 0 Timer TA0 CCI2A capture input 0 1 0 Timer TA0 2 output 1 1 0 S36 X X 1 P1 4 TA0 3 S35 4 P1 4 I O I 0 O 1 0 0 Timer TA0 CCI3A capture input 0 1 0 Timer TA0 3 output...

Page 86: ...VCC P2REN x Pad Logic 1 P2DS x 0 Low drive 1 High drive D From Port Mapping to LCD_B from LCD_B From Port Mapping MSP430F6438 MSP430F6436 MSP430F6435 MSP430F6433 SLAS720D AUGUST 2010 REVISED DECEMBER...

Page 87: ...ital function X 1 19 P2 3 P2MAP3 3 P2 3 I O I 0 O 1 0 Mapped secondary digital function X 1 19 P2 4 P2MAP4 4 P2 4 I O I 0 O 1 0 Mapped secondary digital function X 1 19 P2 5 P2MAP5 5 P2 5 I O I 0 O 1...

Page 88: ...rive D S24 S31 LCDS24 LCDS31 P3IRQ x Interrupt Edge Select Q EN Set P3SEL x P3IES x P3IFG x P3IE x Bus Keeper MSP430F6438 MSP430F6436 MSP430F6435 MSP430F6433 SLAS720D AUGUST 2010 REVISED DECEMBER 2015...

Page 89: ...29 X X 1 P3 3 TA1 2 S28 3 P3 3 I O I 0 O 1 0 0 Timer TA1 CCI2A capture input 0 1 0 Timer TA1 2 output 1 1 0 S28 X X 1 P3 4 TA2CLK SMCLK 4 P3 4 I O I 0 O 1 0 0 S27 Timer TA2 TA2CLK 0 1 0 SMCLK 1 1 0 S2...

Page 90: ...e D S16 S23 LCDS16 LCDS23 P4IRQ x Interrupt Edge Select Q EN Set P4SEL x P4IES x P4IFG x P4IE x Bus Keeper MSP430F6438 MSP430F6436 MSP430F6435 MSP430F6433 SLAS720D AUGUST 2010 REVISED DECEMBER 2015 ww...

Page 91: ...I 0 O 1 0 0 Timer TB0 CCI3A capture input 0 1 0 Timer TB0 3 output 2 1 1 0 S20 X X 1 P4 4 TB0 4 S19 4 P4 4 I O I 0 O 1 0 0 Timer TB0 CCI4A capture input 0 1 0 Timer TB0 4 output 2 1 1 0 S19 X X 1 P4 5...

Page 92: ...rasitic cross currents when applying analog signals An external voltage can be applied to VeREF and used as the reference for the ADC12_A Comparator_B or DAC12_A 4 Setting the P5SEL 0 bit disables the...

Page 93: ...P5 7 Schematic Table 6 55 Port P5 P5 2 to P5 7 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P5 x x FUNCTION P5DIR x P5SEL x LCDS40 42 P5 2 R23 2 P5 2 I O I 0 O 1 0 na R23 X 1 na P5 3 COM1 S42 3 P...

Page 94: ...r_B CBPD x 0 1 2 Dvss 0 if DAC12AMPx 0 1 if DAC12AMPx 1 2 if DAC12AMPx 1 DAC12AMPx 0 DAC12OPS MSP430F6438 MSP430F6436 MSP430F6435 MSP430F6433 SLAS720D AUGUST 2010 REVISED DECEMBER 2015 www ti com 6 13...

Page 95: ...4 A4 4 P6 4 I O I 0 O 1 0 0 n a n a CB4 X X 1 n a n a A4 2 3 X 1 X n a n a P6 5 CB5 A5 5 P6 5 I O I 0 O 1 0 0 n a n a CB5 X X 1 n a n a A5 2 3 X 1 X n a n a P6 6 CB6 A6 DAC0 6 P6 6 I O I 0 O 1 0 0 X 0...

Page 96: ...0F6436 MSP430F6435 MSP430F6433 SLAS720D AUGUST 2010 REVISED DECEMBER 2015 www ti com 6 13 8 Port P7 P7 2 Input Output With Schmitt Trigger Figure 6 9 Port P7 P7 2 Schematic 96 Detailed Description Cop...

Page 97: ...BYPASS P7 2 XT2IN 2 P7 2 I O I 0 O 1 0 X X XT2IN crystal mode 2 X 1 X 0 XT2IN bypass mode 2 X 1 X 1 P7 3 XT2OUT 3 P7 3 I O I 0 O 1 0 0 X XT2OUT crystal mode 3 X 1 X 0 P7 3 I O 3 X 1 0 1 1 X Don t care...

Page 98: ...0 if DAC12AMPx 0 1 if DAC12AMPx 1 2 if DAC12AMPx 1 DAC12AMPx 0 DAC12OPS MSP430F6438 MSP430F6436 MSP430F6435 MSP430F6433 SLAS720D AUGUST 2010 REVISED DECEMBER 2015 www ti com 6 13 10 Port P7 P7 4 to P7...

Page 99: ...6 I O I 0 O 1 0 0 X 0 Comparator_B input CB10 X X 1 X 0 A14 2 3 X 1 X X 0 DAC12_A output DAC0 X X X 1 1 P7 7 CB11 A15 DAC1 7 P7 7 I O I 0 O 1 0 0 X 0 Comparator_B input CB11 X X 1 X 0 A15 2 3 X 1 X X...

Page 100: ...CC P8REN x Pad Logic 1 P8DS x 0 Low drive 1 High drive D S8 S15 LCDS8 LCDS15 Bus Keeper From module MSP430F6438 MSP430F6436 MSP430F6435 MSP430F6433 SLAS720D AUGUST 2010 REVISED DECEMBER 2015 www ti co...

Page 101: ...3 2 P8 2 I O I 0 O 1 0 0 UCA1TXD UCA1SIMO X 1 0 S13 X X 1 P8 3 UCA1RXD UCA1SOMI S12 3 P8 3 I O I 0 O 1 0 0 UCA1RXD UCA1SOMI X 1 0 S12 X X 1 P8 4 UCB1CLK UCA1STE S11 4 P8 4 I O I 0 O 1 0 0 UCB1CLK UCA1...

Page 102: ...7 Schematic Table 6 60 Port P9 P9 0 to P9 7 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P9 x x FUNCTION P9DIR x P9SEL x LCDS0 7 P9 0 S7 0 P9 0 I O I 0 O 1 0 0 S7 X X 1 P9 1 S6 1 P9 1 I O I 0 O 1...

Page 103: ...0 to P9 7 Pin Functions continued CONTROL BITS OR SIGNALS 1 PIN NAME P9 x x FUNCTION P9DIR x P9SEL x LCDS0 7 P9 7 S0 7 P9 7 I O I 0 O 1 0 0 S0 X X 1 Copyright 2010 2015 Texas Instruments Incorporated...

Page 104: ...utputs enabled 0 1 1 0 Output high Output low Outputs enabled 0 1 1 1 Output high Output high Outputs enabled 1 0 X X Input enabled Input enabled Inputs enabled 0 0 X X Hi Z Hi Z Outputs and inputs di...

Page 105: ...MSP430F6436 MSP430F6435 MSP430F6433 www ti com SLAS720D AUGUST 2010 REVISED DECEMBER 2015 6 13 14 Port J J 0 JTAG Pin TDO Input Output With Schmitt Trigger or Output Figure 6 15 Port J PJ 0 Schematic...

Page 106: ...O 2 I 0 O 1 TDI TCLK 3 4 X PJ 2 TMS 2 PJ 2 I O 2 I 0 O 1 TMS 3 4 X PJ 3 TCK 3 PJ 3 I O 2 I 0 O 1 TCK 3 4 X 1 X Don t care 2 Default condition 3 The pin direction is controlled by the JTAG module 4 In...

Page 107: ...Y position 01A10h 2 per unit per unit per unit per unit Test results 01A12h 2 per unit per unit per unit per unit ADC12 calibration tag 01A14h 1 11h 11h 11h 11h ADC12 calibration length 01A15h 1 10h 1...

Page 108: ...eature header pin outs for prototyping Target socket boards are orderable individually or as a kit with the JTAG programmer and debugger included The following table shows the compatible target boards...

Page 109: ...omenclature To designate the stages in the product development cycle TI assigns prefixes to the part numbers of all MSP430 MCU devices and support tools Each MSP430 MCU commercial family member has on...

Page 110: ...to 105 C HT Extreme Temperature Parts 55 C to 150 C Q1 Automotive Q100 Qualified MSP 430 F 5 438 A I ZQW T EP Processor Family Series Optional Temperature Range MCU Platform Packaging Device Type Opt...

Page 111: ...he functional specifications for this device SLAZ324 MSP430F6433 Device Erratasheet Describes the known exceptions to the functional specifications for this device 7 3 Related Links Table 7 1 lists qu...

Page 112: ...complete device failure Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications 7 7 Expor...

Page 113: ...ZR ACTIVE LQFP PZ 100 1000 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 85 M430F6435 MSP430F6435IZQWR ACTIVE BGA MICROSTAR JUNIOR ZQW 113 2500 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR...

Page 114: ...ony Sb based flame retardants Br or Sb do not exceed 0 1 by weight in homogeneous material 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classification...

Page 115: ...80 0 16 4 7 3 7 3 1 5 12 0 16 0 Q1 MSP430F6435IZQWR BGA MI CROSTA R JUNI OR ZQW 113 2500 330 0 16 4 7 3 7 3 1 5 12 0 16 0 Q1 MSP430F6435IZQWT BGA MI CROSTA R JUNI OR ZQW 113 250 180 0 16 4 7 3 7 3 1 5...

Page 116: ...NIOR ZQW 113 2500 336 6 336 6 28 6 MSP430F6433IZQWT BGA MICROSTAR JUNIOR ZQW 113 250 213 0 191 0 55 0 MSP430F6435IZQWR BGA MICROSTAR JUNIOR ZQW 113 2500 336 6 336 6 28 6 MSP430F6435IZQWT BGA MICROSTAR...

Page 117: ......

Page 118: ...UAD FLATPACK 4040149 B 11 96 50 26 0 13 NOM Gage Plane 0 25 0 45 0 75 0 05 MIN 0 27 51 25 75 1 12 00 TYP 0 17 76 100 SQ SQ 15 80 16 20 13 80 1 35 1 45 1 60 MAX 14 20 0 7 Seating Plane 0 08 0 50 M 0 08...

Page 119: ...sponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related inf...

Page 120: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments MSP430F6433IZQWR MSP430F6433IZQWT...

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