Texas Instruments MSP430F643 Series, Manual

Page: 67 / 120

MSP430F6438, MSP430F6436, MSP430F6435, MSP430F6433
www.ti.com SLAS720D – AUGUST 2010 – REVISED DECEMBER 2015
6.12.10 Universal Serial Communication Interface (USCI) (Links to User's Guide: UART
Mode , SPI Mode , I
2
C Mode )
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3-pin or 4-pin) and I
2
C, and asynchronous communication
protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI
module contains two portions, A and B.
The USCI_An module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, or IrDA.
The USCI_Bn module provides support for SPI (3-pin or 4-pin) or I
2
C.
The MSP430F643x series includes two complete USCI modules (n = 0 to 1).
6.12.11 Timer TA0 (Link to User's Guide)
Timer TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers (see Table 6-12 ).
TA0 can support multiple capture/compares, PWM outputs, and interval timing. TA0 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
capture/compare register.
Table 6-12. Timer TA0 Signal Connections
INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER
MODULE
INPUT INPUT OUTPUT OUTPUT
BLOCK
PZ ZQW PZ ZQW
SIGNAL SIGNAL SIGNAL SIGNAL
34-P1.0 L5-P1.0 TA0CLK TACLK
ACLK ACLK
Timer NA NA
SMCLK SMCLK
34-P1.0 L5-P1.0 TA0CLK TACLK
35-P1.1 M5-P1.1 TA0.0 CCI0A 35-P1.1 M5-P1.1
DV
SS
CCI0B
CCR0 TA0 TA0.0
DV
SS
GND
DV
CC
V
CC
36-P1.2 J6-P1.2 TA0.1 CCI1A 36-P1.2 J6-P1.2
40-P1.6 J7-P1.6 TA0.1 CCI1B 40-P1.6 J7-P1.6
CCR1 TA1 TA0.1
ADC12_A (internal)
DV
SS
GND
ADC12SHSx = {1}
DV
CC
V
CC
37-P1.3 H6-P1.3 TA0.2 CCI2A 37-P1.3 H6-P1.3
41-P1.7 M7-P1.7 TA0.2 CCI2B 41-P1.7 M7-P1.7
CCR2 TA2 TA0.2
DV
SS
GND
DV
CC
V
CC
38-P1.4 M6-P1.4 TA0.3 CCI3A 38-P1.4 M6-P1.4
DV
SS
CCI3B
CCR3 TA3 TA0.3
DV
SS
GND
DV
CC
V
CC
39-P1.5 L6-P1.5 TA0.4 CCI4A 39-P1.5 L6-P1.5
DV
SS
CCI4B
CCR4 TA4 TA0.4
DV
SS
GND
DV
CC
V
CC
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