MSP430F6438, MSP430F6436, MSP430F6435, MSP430F6433
SLAS720D – AUGUST 2010 – REVISED DECEMBER 2015
3
Device Comparison
summarizes the available family members.
Table 3-1. Family Members
(1) (2)
USCI
CHANNEL
CHANNEL
FLASH
SRAM
ADC12_A
DAC12_A
Comp_B
DEVICE
Timer_A
(3)
Timer_B
(4)
USB
I/O
PACKAGE
A:
B:
(KB)
(KB)
(Ch)
(Ch)
(Ch)
UART,
SPI, I
2
C
IrDA, SPI
12 ext,
100 PZ,
MSP430F6438
256
18
5, 3, 3
7
2
2
2
12
No
74
4 int
113 ZQW
12 ext,
100 PZ,
MSP430F6436
128
18
5, 3, 3
7
2
2
2
12
No
74
4 int
113 ZQW
12 ext,
100 PZ,
MSP430F6435
256
18
5, 3, 3
7
2
2
-
12
No
74
4 int
113 ZQW
12 ext,
100 PZ,
MSP430F6433
128
10
5, 3, 3
7
2
2
-
12
No
74
4 int
113 ZQW
(1)
For the most current package and ordering information, see the
Package Option Addendum
in
, or see the TI website at
.
(2)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
.
(3)
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
(4)
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
6
Device Comparison
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