MSP430F6438, MSP430F6436, MSP430F6435, MSP430F6433
SLAS720D – AUGUST 2010 – REVISED DECEMBER 2015
6.12.14 Timer TB0
Timer TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers(see
TB0 supports multiple capture/compares, PWM outputs, and interval timing. TB0 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
capture/compare register.
Table 6-15. Timer TB0 Signal Connections
INPUT PIN NUMBER
DEVICE
MODULE
MODULE
DEVICE
OUTPUT PIN NUMBER
MODULE
INPUT
INPUT
OUTPUT
OUTPUT
BLOCK
PZ
ZQW
PZ
ZQW
SIGNAL
SIGNAL
SIGNAL
SIGNAL
58-P8.0
J11-P8.0
TB0CLK
TB0CLK
P2MAPx
(1)
P2MAPx
(1)
ACLK
ACLK
Timer
NA
NA
SMCLK
SMCLK
58-P8.0
J11-P8.0
TB0CLK
TB0CLK
P2MAPx
(1)
P2MAPx
(1)
50-P4.0
J9-P4.0
TB0.0
CCI0A
50-P4.0
J9-P4.0
P2MAPx
(1)
P2MAPx
(1)
TB0.0
CCI0B
P2MAPx
(1)
P2MAPx
(1)
CCR0
TB0
TB0.0
ADC12 (internal)
DV
SS
GND
ADC12SHSx = {2}
DV
CC
V
CC
51-P4.1
M11-P4.1
TB0.1
CCI1A
51-P4.1
M11-P4.1
P2MAPx
(1)
P2MAPx
(1)
TB0.1
CCI1B
P2MAPx
(1)
P2MAPx
(1)
CCR1
TB1
TB0.1
ADC12 (internal)
DV
SS
GND
ADC12SHSx = {3}
DV
CC
V
CC
52-P4.2
L10-P4.2
TB0.2
CCI2A
52-P4.2
L10-P4.2
P2MAPx
(1)
P2MAPx
(1)
TB0.2
CCI2B
P2MAPx
(1)
P2MAPx
(1)
DAC12_A
(2)
CCR2
TB2
TB0.2
DV
SS
GND
DAC12_0, DAC12_1
(internal)
DV
CC
V
CC
53-P4.3
M12-P4.3
TB0.3
CCI3A
53-P4.3
M12-P4.3
P2MAPx
(1)
P2MAPx
(1)
TB0.3
CCI3B
P2MAPx
(1)
P2MAPx
(1)
CCR3
TB3
TB0.3
DV
SS
GND
DV
CC
V
CC
54-P4.4
L12-P4.4
TB0.4
CCI4A
54-P4.4
L12-P4.4
P2MAPx
(1)
P2MAPx
(1)
TB0.4
CCI4B
P2MAPx
(1)
P2MAPx
(1)
CCR4
TB4
TB0.4
DV
SS
GND
DV
CC
V
CC
55-P4.5
L11-P4.5
TB0.5
CCI5A
55-P4.5
L11-P4.5
P2MAPx
(1)
P2MAPx
(1)
TB0.5
CCI5B
P2MAPx
(1)
P2MAPx
(1)
CCR5
TB5
TB0.5
DV
SS
GND
DV
CC
V
CC
56-P4.6
K11-P4.6
TB0.6
CCI6A
56-P4.6
K11-P4.6
P2MAPx
(1)
P2MAPx
(1)
TB0.6
CCI6B
P2MAPx
(1)
P2MAPx
(1)
CCR6
TB6
TB0.6
DV
SS
GND
DV
CC
V
CC
(1)
Timer functions selectable by the port mapping controller.
(2)
Only on devices with peripheral module DAC12_A.
70
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