Quick Setup Guide
2.3
Notes on Efficiency Measurement Procedure
Output Connections: An appropriate electronic load or high-power system source meter instrument,
specified for operation down to 500 mV, is desirable for loading the UUT. The maximum load current is
specified as 10 A. Be sure to choose the correct wire size when attaching the electronic load. A wire
resistance that is too high will cause a voltage drop in the power distribution path which becomes
significant compared to the absolute value of the output voltage. Connect an electric load positive terminal
(+) to X1 and negative terminal (-) to X2. It is advised that, prior to connecting the load, it be set to sink 0A
to avoid power surges or possible shocks.
Voltage drop across the PWB traces will yield inaccurate efficiency measurements. For the most accurate
voltage measurement at the EVM, use TP14 to measure the input voltage and TP10 to measure the
output voltage.
To measure the current flowing to/from the UUT, use the current meter of the DC power supply/electric
load as long as it is accurate. Some power source ammeters may show offset of several milliamps and
thus will yield inaccurate efficiency measurements. In order to perform very accurate I
q
measurements on
the UUT, disconnect input protective Zener diode D1 by removing the shunt J2 from the board. When
connected, this diode will cause some leakage, especially on high VIN voltages. Also, the output voltage
ADC on the USB Interface Board will load the output of LP8754 with a resistance in order of a hundred of
k
Ω
. The 0-
Ω
resistor between the pads of J11 on the lower left corner of the EVB may also be removed
(see
3
GUI Overview
The evaluation software has the following tabs: Main, Config, and Advanced. The three tabs together
provide the user access to the whole register map of LP8754.
3.1
Main Tab
The Main tab has the elemental controls for the EVM and provides a view to the chip status. Starting from
top, the main controls are:
•
Assert VIOSYS: This checkbox will assert 1.8-V voltage to LP8754 VIOSYS pin. This pin will enable
the chip internal voltage reference and LDO, release POR, and launch OTP read cycle. The VIOSYS
voltage is the reference voltage for the System I
2
C bus.
•
Assert NRST: This checkbox will assert 1.8-V voltage to LP8754 NRST pin. Asserting NRST will
launch power-up sequence.
•
Assert SW Reset: To perform a complete SW reset to the chip, assert and de-assert this checkbox.
See the
for explanation of LP8754 reset scenarios.
•
Assert NSLP: When this bit is asserted it tells LP8754 that the device it is powering is in a high-load
condition state. On LP8754 this effectively prevents the bucks from entering the Low-Power PFM Mode
(ECO).
NOTE:
The recommended start-up sequence for LP8754 is to first assert VIOSYS, then write all
needed configuration bits by using the GUI, and then to assert NRST.
NOTE:
The NRST pin is the reference for the DVS (Dynamic Voltage Scaling) bus (that is,
SmartReflex™ bus). NRST needs to be asserted before the chip will acknowledge any
transmission on the DVS bus.
The Bucks section provides status information for all the 6 buck cores. The Mode field provides
information on each of the buck core and can have any of the values given in
7
SNVU369 – August 2014
The LP8754 Evaluation Module
Copyright © 2014, Texas Instruments Incorporated
