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LP8754 Schematic

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LP8754 Schematic

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The LP8754 Evaluation Module

SNVU369 – August 2014

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Copyright © 2014, Texas Instruments Incorporated

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Summary of Contents for LP8754EVM

Page 1: ...the LP8754EVM Evaluation Module User s Guide Literature Number SNVU369 August 2014 SmartReflex is a trademark of Texas Instruments Incorporated All other trademarks are the property of their respective owners ...

Page 2: ...up 6 2 3 Notes on Efficiency Measurement Procedure 7 3 GUI Overview 7 3 1 Main Tab 7 3 2 Other Tabs and Menus 8 3 3 Console 9 4 Bill of Materials 10 5 Board Layout 11 6 LP8754 Schematic 14 2 Table of Contents SNVU369 August 2014 Submit Documentation Feedback Copyright 2014 Texas Instruments Incorporated ...

Page 3: ...and inductors are connected together with large copper area 12 7 2nd Layer GND GND plane kept intact under the high current traces to provide shortest possible return path for high frequencies 12 8 3rd Layer VIN Plane kept intact around the LP8754 Below the LP8754 is small ground area connecting the microvias from 3rd to bottom layer and buried vias from 2nd to 3rd layer 12 9 Bottom Layer and Silk...

Page 4: ...design documentation that includes schematics and parts list Figure 1 LP8754EVM The evaluation module consists of two PCB boards the LP8754 Evaluation Board and the USB Interface Board The boards are of the same size and the LP8754 board is stacked on top of the USB Interface Board 2 Quick Setup Guide Many of the components on the LP8754 are susceptible to damage by electrostatic discharge ESD Cus...

Page 5: ...ard drive then unzip this folder Make sure the USB Interface Board is connected to the Evaluation Board and connect the USB Interface Board to the PC with the USB cable Refer to Figure 1 1 With the power supply disconnected from the unit under test UUT open the un zipped folder and click on lp8754_nnn exe nnn is the version number to start the software 2 On the Evaluation SW window bottom right co...

Page 6: ...e terminal to VIN and negative terminal to GND on UUT X3 Power in terminal block Check that jumpers on the boards are set as shown in Figure 1 factory default jumper configuration Set power supply output ON and then continue with the following steps 1 On Evaluation software GUI click on Assert VIOSYS See Figure 3 Marking 1 2 Click on Assert NRST See Figure 3 Marking 2 3 Click on Read Registers but...

Page 7: ... of J11 on the lower left corner of the EVB may also be removed see Section 6 3 GUI Overview The evaluation software has the following tabs Main Config and Advanced The three tabs together provide the user access to the whole register map of LP8754 3 1 Main Tab The Main tab has the elemental controls for the EVM and provides a view to the chip status Starting from top the main controls are Assert ...

Page 8: ... register s If not checked the user can update the chip registers to correspond the configuration selected on the GUI by clicking Write Registers If Poll Status is selected the software sends a query to the LP8754 at a fixed interval in order to detect the status of the chip including operation mode multi phase status and output current If not selected user can read the registers by applying Read ...

Page 9: ...called with no parameter treated as query and current selection is returned 0x address data I2 C read or write command or addr value address bits data examples 0x12 0xaa 0x12 7 1 0x12 3 0 15 The console supports use of scripts If a text file containing commands supported by the console is stored in the same folder with the evaluation software executable then the script can be launched from the con...

Page 10: ...amtec Inc QTE 020 01 L D A 1 Header TH 100mil 2x2 Gold plated J7 Samtec Inc TSW 102 07 G D 1 230 mil above insulator Inductor Multilayer Ferrite 470nH 2 7A L0 L1 L2 L3 L4 L5 MuRata LQM21PNR47MGH 6 0 04 ohm SMD RES 0 01Ω 1 3W 2512 High Power R1 Bourns CRA2512 FZ R010ELF 1 Current Sense Chip Resistor R7 R8 R9 RES 1 8kΩ 5 0 1W 0603 Vishay Dale CRCW06031K80JNEA 3 R10 R11 R12 R13 R14 R15 RES 0 ohm 5 0 ...

Page 11: ...and bottom layers Top layer contains the large copper area connecting the VOUT pads of the inductors and output capacitors together and to the load terminals 2nd layer is the ground plane and 3rd layer is the VIN plane Also the bottom layer contains large copper area filled with ground Input capacitors are placed as close to the LP8754 as possible for keeping the critical VIN and GND traces short ...

Page 12: ... plane kept intact under the LP8754 and routed on top layer GND nets are the high current traces to provide shortest possible return connected to the GND plane 2nd layer with microvias path for high frequencies VIN nets are connected to the VIN plane 3rd layer with vias in pads of the input capacitors VOUT pads of the output capacitors and inductors are connected together with large copper area 12...

Page 13: ...rea input capacitors C32 and C33 GND filling in bottom layer connecting the microvias from 3rd to bottom layer and for sinking heat through the GND vias buried vias from 2nd to 3rd layer Figure 10 3D View Showing the LP8754 and Nearest Components 13 SNVU369 August 2014 The LP8754 Evaluation Module Submit Documentation Feedback Copyright 2014 Texas Instruments Incorporated ...

Page 14: ...LP8754 Schematic www ti com 6 LP8754 Schematic 14 The LP8754 Evaluation Module SNVU369 August 2014 Submit Documentation Feedback Copyright 2014 Texas Instruments Incorporated ...

Page 15: ...ring the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty If TI elects to repair or replace such EVM TI shall have a reasonable time to repair such EVM or provide replacements Repaired EVMs shall be warranted for the remainder of the original warranty period Replaced EVMs shall be warranted for a new full ninety 90 day warranty period 3 ...

Page 16: ... by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated Antenna types not included in this list having a gain greater than the maximum gain indicated for that type are strictly prohibited for use with this device Concernant les EVMs avec antennes détachables Conformément à la rég...

Page 17: ... connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation even with the inputs and outputs kept within the specified allowable ranges some circuit components may have elevated case temperatures These components include but are not limited to linear regulators switching transistors pass transistors cu...

Page 18: ...F REMOVAL OR REINSTALLATION ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES RETESTING OUTSIDE COMPUTER TIME LABOR COSTS LOSS OF GOODWILL LOSS OF PROFITS LOSS OF SAVINGS LOSS OF USE LOSS OF DATA OR BUSINESS INTERRUPTION NO CLAIM SUIT OR ACTION SHALL BE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED 8 2 Specific Limitations IN NO EVENT SHALL T...

Page 19: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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