Texas Instruments LP8754EVM, User Manual, Page: 3 / 19

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List of Figures
1 LP8754EVM
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2 Evaluation Software Graphical User Interface (GUI) When USB Board Connected
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3 Evaluation Software GUI Showing Steps Needed to Power up the LP8754
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4 Top view of the LP8754EVM
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5 Component placement near the LP8754. Capacitors marked with X are optional.
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6 Top-layer. Input capacitors are placed close to the LP8754 and routed on top layer. GND nets are
connected to the GND plane (2nd layer) with microvias. VIN nets are connected to the VIN plane (3rd
layer) with vias in pads of the input capacitors. VOUT pads of the output capacitors and inductors are
connected together with large copper area.
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7 2nd Layer (GND). GND plane kept intact under the high current traces to provide shortest possible
return path for high frequencies.
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8 3rd Layer (VIN). Plane kept intact around the LP8754. Below the LP8754 is small ground area
connecting the microvias (from 3rd to bottom layer) and buried vias (from 2nd to 3rd layer).
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9 Bottom-Layer and Silk. Footprints for optional input capacitors C32 and C33. GND filling in bottom layer
for sinking heat through the GND vias.
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10 3D View Showing the LP8754 and Nearest Components
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List of Tables
1 Mode Information
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2 I
2
C-Compatible Bus Support
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3 Console Macros
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3 SNVU369 – August 2014 List of Figures
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