When INT_EN = 1, any live status flag which occurs will latch to the INTR Latched bit columns. These will
remain asserted until the
Clear Latched Bits
button is pressed. This gives additional insight into the behavior of
the device.
Press the
Soft-chip reset
button in the toolbar to reset the device and restart the lock.
Figure 6-8. Status Page
6.3 Using the Input Page
The Input page provides a high-level view of all the inputs for the device, the APLL frequencies, and DPLL
frequencies of the device.
When the DPLL dividers and loop filter are calculated by running the script in step 7 on the start page, this page
displays the DPLL divider values which set the DPLL frequency. Here it is shown that the DPLL frequency is the
exact desired frequency.
Each DPLL supports two sets of DPLL dividers which can be selected. At this time, the tool calculates the divider
for FB Config 1 only. To use two different feedback dividers, the following procedure should be preformed:
1. Div #1 settings may be copied into Div #2 settings and selected for use by the
DPLL Div Select control
.
2. The references that require the Div #2 settings should be set to FB Config 2.
3. A second calculation can be run (re-perform a run script, step 7 on start page, of the DPLL) which will
repopulate Div #1 settings with the new values for FB Config 1.
a. Div #2 settings will remain the same as the ones initial copied over in step 1.
Appendix A - TICS Pro LMK5B33216 Software
36
LMK5B33216EVM User's Guide
SNAU263A – FEBRUARY 2022 – REVISED JULY 2022
Copyright © 2022 Texas Instruments Incorporated