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Backplane Board
2-5
GTLP EVM Board Typical Test and Setup Configuration
Figure 2–4. GTLP EVM Backplane Block Diagram
Backplane Overview
Slot 1
Slot 2
Slot 3
Slot 4
Slot 5
Slot 6
Slot 7
Slot 8
Slot 9
Slot 10
Slot 1
1
Slot 12
Slot 13
Slot 14
Slot 15
Slot 16
Slot 17
Slot 18
Slot 19
Slot 20
É
É
É
É
É
É
É
É
É
X
X
É
É
É
É
É
É
É
É
É
Clock Generator
X = Termination Card on Back of Connector
Table 2–1. GTLP EVM Group Assignment
Group 6
Group 5
Group 4
Group 3
Group 2
Group 1
2 slots
4 slots
8 slots
12 slots
16 slots
20 slots
P1-1 to P1-2
P1-1 to P1-4
P1-1 to P1-8
P1-1 to P1-12
P1-1 to P1-16
P1-1 to P1-20
A single GTLP clock line that runs from P1-1 to P1-20 is used in the
source-synchronous transfer mode.
The GTLP clock and the data lines from groups 2 through 6 have fixed,
on-board, 25-
Ω
termination resistors. Group 1 data lines terminate on plug-in
cards on the back of the backplane board at P1-1B and P1-20B. This provides
a way to vary the termination resistance or demonstrate other termination
techniques.
The design also uses a system clock that is generated on the clock-driver
board plugged into P3. This system clock is distributed to all 20 slots
simultaneously and is used as the system master timing in the system-clock
mode. Using a separate card for clock generation and distribution is not an
industry standard, but it provides flexibility in using this demonstration board.
Summary of Contents for GTLP
Page 1: ...June 2001 Standard Linear Logic GTLP Evaluation Module EVM User s Guide ...
Page 2: ...Printed in U S A 0601 SCEA023 ...
Page 3: ...GTLP Evaluation Module EVM User s Guide SCEA023 June 2001 Printed on Recycled Paper ...
Page 12: ...Tables x ...
Page 26: ...Connectors 2 10 Figure 2 7 AMP Single Line Model Data Sheet ...
Page 65: ...Monitored Waveforms 4 8 ...
Page 71: ...Damage to the Daughter Cards 5 6 ...
Page 79: ...Board Layouts and Schematics A 8 Figure A 4 Backplane Schematic ...
Page 81: ...Board Layouts and Schematics A 10 Figure A 6 Driver Card Schematic ...