Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Receiver Card (R2) Group 1 LVTTL Data Out (Ch2)
4-5
Waveform Measurement and Interpretation
4.4
Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and
Receiver Card (R2) Group 1 LVTTL Data Out (Ch2)
Figure 4–4 shows the probe hookup and O-Scope output for Case 4. The
LVTTL data input goes to the SN74GTLPH1655 driving device A-port input,
and the LVTTL data output of the SN74GTL1655 receiving device goes to
A port in slot 2. Because the GTLP EVM is clocked using the central system
clock (i.e., clock arrives at all daughter cards at the same time) the total delay
from the LVTTL data input on slot 1 to the LVTTL data output on slot 2 is the
sum of one clock cycle (20 ns), the setup time on the driver card (
∼
9 ns), and
the propagation delay of the GTLPH1655 CLK to A of about 3 ns. The GTLP
EVM driver card is set up to transmit sixteen bits of data and then wait eight
cycles before transmitting again. This allows the technician to determine the
total delay. In this case, assuming the waveform in Ch1 had just started, the
total delay is about 32 ns.
Figure 4–4. Case 4: D1 Data Pattern (Ch1) and R2 Group 1 LVTTL Data Out (Ch2)
LVTTL
Data
Input
LVTTL
Data
Output
Total Propagation Delay
Summary of Contents for GTLP
Page 1: ...June 2001 Standard Linear Logic GTLP Evaluation Module EVM User s Guide ...
Page 2: ...Printed in U S A 0601 SCEA023 ...
Page 3: ...GTLP Evaluation Module EVM User s Guide SCEA023 June 2001 Printed on Recycled Paper ...
Page 12: ...Tables x ...
Page 26: ...Connectors 2 10 Figure 2 7 AMP Single Line Model Data Sheet ...
Page 65: ...Monitored Waveforms 4 8 ...
Page 71: ...Damage to the Daughter Cards 5 6 ...
Page 79: ...Board Layouts and Schematics A 8 Figure A 4 Backplane Schematic ...
Page 81: ...Board Layouts and Schematics A 10 Figure A 6 Driver Card Schematic ...