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Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and Driver Card (D1) Latch Clock (Ch2)
4-2
4.1
Timing Relationship of Driver Card (D1) Data Pattern (Ch1) and
Driver Card (D1) Latch Clock (Ch2)
Figure 4–1 shows the probe hookup and related O-Scope output for Case 1.
The LVTTL latch clock signal goes to the SN74GTLPH1655 driving device
CLK pin, and the LVTTL data signal goes to the A-port input pin, specifically
the Group 1, bit 1 data signal.
Figure 4–1. Case 1: D1 Data Pattern (Ch1) and D1 Latch Clock (Ch2)
LVTTL
Data
Input
LVTTL
Latch-Clock
Input
Summary of Contents for GTLP
Page 1: ...June 2001 Standard Linear Logic GTLP Evaluation Module EVM User s Guide ...
Page 2: ...Printed in U S A 0601 SCEA023 ...
Page 3: ...GTLP Evaluation Module EVM User s Guide SCEA023 June 2001 Printed on Recycled Paper ...
Page 12: ...Tables x ...
Page 26: ...Connectors 2 10 Figure 2 7 AMP Single Line Model Data Sheet ...
Page 65: ...Monitored Waveforms 4 8 ...
Page 71: ...Damage to the Daughter Cards 5 6 ...
Page 79: ...Board Layouts and Schematics A 8 Figure A 4 Backplane Schematic ...
Page 81: ...Board Layouts and Schematics A 10 Figure A 6 Driver Card Schematic ...