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June 2001

Standard Linear & Logic

GTLP Evaluation Module

(EVM)

User’s Guide

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Summary of Contents for GTLP

Page 1: ...June 2001 Standard Linear Logic GTLP Evaluation Module EVM User s Guide ...

Page 2: ...Printed in U S A 0601 SCEA023 ...

Page 3: ...GTLP Evaluation Module EVM User s Guide SCEA023 June 2001 Printed on Recycled Paper ...

Page 4: ...design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such products or services might be or are used TI s publicationof information regarding any third party s products or services does not constitute...

Page 5: ...vices How to Use This Manual This document contains the following chapters Chapter 1 Introduction Chapter 2 GTLP EVM Board Typical Test and Setup Configuration Chapter 3 Oscilloscope Operation Chapter 4 Waveform Measurement and Interpretation Chapter 5 Troubleshooting Appendix A Bill of Materials Schematics Board Layouts and Suggested Specifications ...

Page 6: ...ng carefully FCC Warning This equipment is intended for use in a laboratory test environment only It generates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in oth...

Page 7: ...on Cards 2 15 2 8 Bottom Compartment 2 17 2 9 Measurement Equipment 2 18 2 10 Clock Cards 2 19 2 11 Driver Cards 2 21 2 11 1 Single Bit Selection 2 23 2 11 2 Edge Rate Control 2 24 2 11 3 Source Synchronous Clock System Clock Selection 2 25 2 12 Receiver Cards 2 26 2 13 Backplane Setup 2 29 2 13 1 Insertion of Clock Cards 2 29 2 13 2 Insertion of Clock Crystals 2 31 2 13 3 Insertion of Termination...

Page 8: ...a In Ch2 4 4 4 4 Timing Relationship of Driver Card D1 Data Pattern Ch1 and Receiver Card R2 Group 1 LVTTL Data Out Ch2 4 5 4 5 Timing Relationship of Receiver Card R2 Group 1 GTLP Data In Ch1 and Receiver Card R20 Group 1 GTLP Data In Ch2 4 6 4 6 Monitored Waveforms 4 7 5 Troubleshooting 5 1 5 1 Spare Parts 5 2 5 2 Replacing 5 A Fuse F2 5 3 5 3 Replacing 2 5 A Fuse F1 5 4 5 4 Damage to the Daught...

Page 9: ... 2 17 GTLP EVM Clock Card 2 19 2 18 GTLP EVM Driver Daughter Card 2 22 2 19 Bit Selection for Normal Data Pattern Left Signal Held Low Center or Signal Held High Right 2 23 2 20 ERC Bit Selection Jumper Set for Slow Left or Fast Right Rate 2 24 2 21 JB2 Set to Source Synchronous Clock Left or System Clock Right Operation 2 25 2 22 GTLP EVM Monitored Receiver Card 2 28 2 23 AMP Z PACK 2 mm 55 Pin H...

Page 10: ...se 5 R2 Group 1 GTLP Data In Ch1 and R20 Group 1 GTLP Data In Ch2 4 6 4 6 GTLP Backplane Waveforms at 23 MHz Clock Frequency 4 7 4 7 GTLP Monitor Test Point Waveforms at 23 MHz Clock Frequency 4 7 5 1 Spare Fuses and Jumpers 5 2 5 2 Fuse F2 Left and Removal Procedure Right 5 3 5 3 Fuse F1 5 4 A 1 Backplane Layout Front Side A 5 A 2 Backplane Layout Back Side A 6 A 3 Driver Card and Receiver Card C...

Page 11: ...up Assignment 2 6 2 2 GTLP EVM Backplane Eight Layer Stackup 2 7 2 3 GTLP EVM Group 1 Bits 1 Through 8 Trace Impedance 2 8 2 4 Termination Card Stackup 2 17 2 5 Clock Card Stackup 2 21 2 6 Driver Card Stackup 2 22 2 7 Receiver Card Stackup 2 27 ...

Page 12: ...Tables x ...

Page 13: ...sed on drive capability live insertion capability data throughput noise margin backward compatibility and bus configuration The purpose of the GTLP EVM is to demonstrate the performance of the TI GTLP product portfolio in a best in class high performance backplane The backplane enables users to observe the effects of different kinds of terminations changing load conditions due to different spacing...

Page 14: ...imized to support high speed operation up to 100 MHz Thus understanding impedance control and transmission line effects are crucial when designing high speed boards Some of the advanced features offered by this board include The backplane printed circuit board PCB is designed for high speed signal integrity while the daughter card is designed with integral measurement points for easily measuring s...

Page 15: ...t comprises the following major parts components of which are listed in Appendix A 1 GTLP EVM Bill of Materials GTLP EVM kit documentation this document SCEA023 Backplane Clock driver card Termination card Monitored receiver card Monitored driver card Unmonitored receiver card ...

Page 16: ...y The GTLP EVM kit is not available for resale but can be obtained and used for short periods of time by contacting the GTLP team at GTLP list ti com There are six locations worldwide where GTLP EVMs can be obtained Europe China Korea Japan and the Americas 2 ...

Page 17: ...to evaluate different transceivers that will be available in the future Topic Page 2 1 GTLP EVM Case 2 2 2 2 Top Tray 2 3 2 3 Backplane Board 2 4 2 4 Connectors 2 8 2 5 Power Supply 2 11 2 6 Clock Crystals 2 14 2 7 Termination Cards 2 15 2 8 Bottom Compartment 2 17 2 9 Measurement Equipment 2 18 2 10 Clock Cards 2 19 2 11 Driver Cards 2 21 2 12 Receiver Cards 2 26 2 13 Backplane Setup 2 29 Chapter...

Page 18: ...handle see Figure 2 1 The handle locks in position and can be extended or retracted by pressing the release on the underside of the handle Figure 2 1 GTLP EVM Case The case is suitable for air transportation and has the combination lock set at 394 To lock the case rotate one or more of the dials from the opening combination ...

Page 19: ... top tray fits snuggly in the GTLP EVM case see Figure 2 2 and holds the backplane board power supply extra clock crystals and extra termination cards in place The tray is electrostatic protective foam that holds the backplane board during demonstrations Figure 2 2 GTLP EVM Top Tray ...

Page 20: ... and 1 clock bit on stripline transmission lines Figure 2 3 GTLP EVM Backplane Board This backplane board is constructed uniquely of six groups of eight data bits each to study the effect of different backplane lengths and driver receiver placements Group 1 consists of all 20 slots but subsequent groups move to the left see Figure 2 4 and have a reduced number of slots as listed in Table 2 1 ...

Page 21: ...to P1 20 A single GTLP clock line that runs from P1 1 to P1 20 is used in the source synchronous transfer mode The GTLP clock and the data lines from groups 2 through 6 have fixed on board 25 Ω termination resistors Group 1 data lines terminate on plug in cards on the back of the backplane board at P1 1B and P1 20B This provides a way to vary the termination resistance or demonstrate other termina...

Page 22: ...Nelco N4000 13 with a dielectric constant 50 resin contents of 3 80 100 MHz Table 2 2 GTLP EVM Backplane Eight Layer Stackup Trace Name Use Layer Copper Weight oz Physical Representation Dielectric Height in Dielectric Name Top Regulator power bypass capacitor termination 1 0 5 0 004 B stage Internal signal 2 Clock distribution signal 2 1 0 004 Core Ground plane Ground plane 3 1 0 004 B stage Inte...

Page 23: ... 148 147 142 Co pF in 1 81 2 95 2 94 2 96 2 94 3 12 1 77 2 99 Trace Impedance With Only Connectors Zo Ω 62 7 37 5 37 36 3 37 1 37 9 58 5 36 8 tpd ps in 240 177 175 180 183 185 208 183 Trace Impedance Under Full Load Zo Ω 26 6 17 7 17 9 17 5 17 9 18 24 8 17 7 tpd ps in 564 377 362 373 377 390 493 382 Note the difference in fully loaded trace impedance between trace bit 1 and bit 7 D1 and D7 and the...

Page 24: ...ThereisonlyoneB lengthpinbecauseBIASVCC can be distributed to all four GTLP devices on the board The pin lengths of pins K and T are identical to those of pins A and C on the card side but they protrude through the backplane board providing connection to the termination cards that are on the reverse side Initial testing revealed that this pin configuration was unacceptable for actual operationbeca...

Page 25: ...Connectors 2 9 GTLP EVM Board Typical Test and Setup Configuration Figure 2 6 AMP Pin Lengths X U V are used only for cross connect applications Not all versions are tooled ...

Page 26: ...Connectors 2 10 Figure 2 7 AMP Single Line Model Data Sheet ...

Page 27: ...oard until the cards have been inserted during the initial setup because the clock card is not hot insertable The termination daughter cards and clock crystals are live insertable and can be inserted and removed to change position values during testing without disconnecting the power supply Figure 2 8 Power Supply Left and Backplane Connection Right The 24 Vdc is reduced to 5 V 1 A by the Lambda P...

Page 28: ... 2 9 1 5 V VTT Linear Regulator Unitrode offers two devices UC382 and UC385 that can be used in place of the LT1083CP They offer low dropout at a given current 500 mV dropout maximum at 5 A the ability to handle transients with tight regulation high current capability fast transient response separate bias and Vin pins and 5 pin TO220 and TO263 packages with Kelvin sensing UC382 provides 3 A capaci...

Page 29: ...Power Supply 2 13 GTLP EVM Board Typical Test and Setup Configuration Figure 2 10 Power Supply LED Indicators ...

Page 30: ... and 100 MHz are included with the kit One crystal can be installed on each clock card with the others stored in the clock crystal tube see Figure 2 11 Figure 2 11 Clock Crystal on Card Left and Stored in Tube Right If you plan to store the clock driver card with the crystal installed insert the crystal far enough so that the leads barely protrude on the opposite side see Figure 2 12 This prevents...

Page 31: ...r 50 Ω One bypass capacitor is mounted with every other termination resistor to limit voltage fluctuations The termination cards provide a method of varying the termination resistance to only Group 1 data lines These termination resistors connect to the VTT supply 1 5 V because GTLP levels are used Figure 2 13 Termination Card Location Left and Close Up View Right Match Dots Connector Key Can be r...

Page 32: ...ave 25 Ω fixed termination resistors due to space limitations and have one bypass capacitor for every four termination resistors The 25 Ω termination is optimized for estimated 25 Ω loaded line impedance The termination cards can remain installed on the backplane board or be removed during storage and transit Both termination cards can be stored in the same slot in the tray see Figure 2 14 or stor...

Page 33: ...Area Monitored Receiver Cards Unmonitored Receiver Cards Clock Cards Empty Slots Oscilloscope Storage Driver Cards There are 2 clock cards 19 unmonitored receiver cards 3 monitored receiver cards and 2 driver cards in every GTLP EVM kit Store the cards as shown in Figure 2 15 with the 2 clock cards top left followed by 10 unmonitored receiver cards 3 monitored receiver cards middle left followed b...

Page 34: ... prevent damage to the buttons during transit The probes can be stored on top of the O Scope as shown or alongside depending on the amount of space in either location The O Scope is not included with the loaned EVM kits Chapter 3 Oscilloscope Operation discusses O Scope setup and operation and is included to provide assistance to TI product marketing engineers and technical sales representatives w...

Page 35: ...plug in half can oscillator for a reference to two CDC2586 phase locked loop clock drivers These two drivers provide the 20 system clocks used on the backplane The CDC2586 supports a maximum frequency of 100 MHz The clock card has one subminiature B connector SMB as specified by MIL C 39012 coaxial connector specification test point to monitor the oscillator output Figure 2 17 GTLP EVM Clock Card ...

Page 36: ...ckup Trace Name Use Layer Copper Weight oz Physical Representation Dielectric Height in Dielectric Name Top Data signal 1 0 5 0 004 B stage VCC plane VCC plane 2 1 0 004 Core Ground plane Ground plane 3 1 0 004 B stage Bottom Data signal 4 0 5 ...

Page 37: ... devices are hardwired for clocked storage in the A to B direction Data is transmitted on the rising edge of the system clock The driver card is a six layer PCB with two signal layers a VCC plane a ground plane then two signal layers Stackup is shown in Table 2 6 Table 2 6 Driver Card Stackup Trace Name Use Layer Copper Weight oz Physical Representation Dielectric Height in Dielectric Name Top Dat...

Page 38: ... to all SN74GTLPH1655 LVTTL A port inputs There are no LVTTL group bit monitor points because the card always is driven Monitor points along the right edge are GTLP Group 1 2 3 4 5 and 6 The following signals are monitored TP1 GTLP level Group 1 bit 1 TP2 GTLP level Group 2 bit 1 TP3 GTLP level Group 3 bit 1 TP4 GTLP level Group 4 bit 1 TP5 GTLP level Group 5 bit 1 TP6 GTLP level Group 6 bit 1 TP7...

Page 39: ...or set the signal high see Figure 2 19 The JB1 jumper is stored on the lowest pin see Figure 2 19 when set high to prevent losing it The following options are available JB1 1 2 shorted Group 1 bit 1 normal data pattern JB1 2 3 shorted Group 1 bit 1 held low JB1 open Group 1 bit 1 held high Figure 2 19 Bit Selection for Normal Data Pattern Left Signal Held Low Center or Signal Held High Right JB1 J...

Page 40: ... rate control ERC pin held at 3 3 V slow or GND fast The ERC is set by the JB3 jumper located below the bit selection jumper and has two positions not connected is slow and shorted is fast see Figure 2 20 The following ERC options are available JB3 open Slow edge rate JB3 shorted Fast edge rate Figure 2 20 ERC Bit Selection Jumper Set for Slow Left or Fast Right Rate JB3 Jumper ...

Page 41: ...te in conjunction with the JB3 selection Source synchronous clock operation provides a relative clock to all receiver cards which removes the flight time delay restrictions required when an absolute system clock is used The flight time delay depends primarily on bus length and bus loading The driver card uses JB2 to select the transfer mode of operation and to drive the MODESEL line Source synchro...

Page 42: ...rd causes Receiver cards have GTLP devices hardwired for clocked storage in the B to A direction Data is latched on the rising edge of the GTLP latch clock The latch clock comes from the system clock when the MODESEL line is high and from the GTLP clock when the MODESEL line is low The receiver card is a six layer PCB with two signal layers a VCC plane a ground plane then two signal layers The GTL...

Page 43: ...SN74GTLP1394 driver card along the 1 bit clock trace on the backplane to the SN74GTLP1394 receiver card that converts it back to LVTTL logic levels The monitored receiver card has SMB jacks to monitor selected signals TP1 GTLP level Group 1 bit 1 TP2 GTLP level Group 2 bit 1 TP3 GTLP level Group 3 bit 1 TP4 GTLP level Group 4 bit 1 TP5 GTLP level Group 5 bit 1 TP6 GTLP level Group 6 bit 1 TP7 LVTT...

Page 44: ...L1655 and SN74GTLPH1655 are identical except for the B port output edge rate slew and B port Cio Because the GTLP signals only are received by the receiver cards it is essentially immaterial which devices are used on the receiver cards because both have the same differential input except for the difference in B port Cio which is 6 pF typical and 8 pF maximum for the SN74GTL1655 and 8 5 pF typical ...

Page 45: ...ane connectors are keyed in the center and do not allow improper insertion The clock card should be inserted or removed from the backplane only after power has been disconnected to prevent damage to the CDC components Figure 2 23 AMP Z PACK 2 mm 55 Pin HM Male Left and Female Right Clock Card Connectors Connector Key Connector Key Figure 2 24 shows the mating sequence When mated the connectors sho...

Page 46: ...y inserted with the CDC components and the clock crystal facing away from the backplane connectors and daughter cards Yellow dots are located on the connector and the card to help ensure proper orientation Figure 2 25 right shows the card improperly inserted Figure 2 25 Clock Card Properly Left and Improperly Right Inserted Match Dots ...

Page 47: ...ly on the clock card by pulling off one crystal and inserting the new crystal see Figure 2 26 The leads can be bent gently to ease insertion The clock crystal need not be inserted fully flush with the card for proper operation In fact this condition is preferred if the clock card is stored with the crystal inserted otherwise the foam liner can bend the exposed leads Figure 2 26 Clock Crystal Remov...

Page 48: ...ure 2 27 Termination Card Keying Keying Be sure that the red dot on the male connector and the card are facing each other to prevent improper operation Both termination card components face the same direction toward slot 20 so the key to proper operation is to inspect for the keying and line up the red dots see Figure 2 28 If the backplane is not working the proper orientation of the termination c...

Page 49: ...ard should be used at any one time There is no bus contention damage if multiple driver cards are in operation at the same time this is one key benefit from using the GTLP open drain technology Figure 2 29 shows the connector keying that allows the cards to be placed on the connector in only one direction When inserted properly the component side of the card faces slot 1 Figure 2 29 Driver and Rec...

Page 50: ...own see Figure 2 31 with very little side to side motion The components are facing left towards slot 1 the power supplies are on the top right and the Group 1 6 markings are on the bottom left The card in Figure 2 31 is being inserted into slot 20 Figure 2 31 Proper Connector Mating Sequence Left to Right Figure 2 32 shows the connectors properly mated ...

Page 51: ...Backplane Setup 2 35 GTLP EVM Board Typical Test and Setup Configuration Figure 2 32 Connectors Properly Mated ...

Page 52: ...3 1 Oscilloscope Operation Topic Page 3 1 Oscilloscope Setup 3 2 3 2 Measurements 3 3 Chapter 3 ...

Page 53: ...ould be sufficient for most investigations done with the demonstration backplane Figure 3 1 Tektronix O Scope Front Left and Top Right SMB adapters see Figure 3 2 are needed to properly mate Tektronix probes with the test points These adapters are custom built for the Tektronix O Scope probes and are not normally included in the GTLP EVM Figure 3 2 O Scope Probe Monitor Point Adapters ...

Page 54: ...her probe into channel 2 CH 2 of the O Scope and connect the opposite end to the desired monitor point see Figures 3 1 and 3 3 Chapter 4 Waveform Measurement and Interpretation discusses which monitor points should be used and why Figure 3 3 Simple Test Measurement Connection Press the ON STBY button on the O Scope see Figure 3 4 and press the CH 1 or CH 2 button Figure 3 4 Turn On O Scope Left an...

Page 55: ...Measurements 3 4 Waveforms similar to those in Figure 3 5 depending on how the O Scope presets were set are displayed In Figure 3 5 CH 2 is selected Figure 3 5 O Scope Display ...

Page 56: ...ng is the same for both channels and is independent of channel selection Figure 3 6 Timing Adjustment To adjust the voltage y or vertical axis press the top or bottom of the VOLTS DIV button see Figure 3 7 An example of the results is shown for Ch2 at 1 V center and Ch2 at 2 V right Voltage adjustment is independent of channels which are selected by pressing either the CH 1 or the CH 2 button Figu...

Page 57: ...then press Trigger Source to display a submenu In the submenu select Ch1 Ch2 or Ext DMM by repeatedly pressing the same Trigger Source button After the appropriate trigger is selected press the CLEAR MENU button to restore the O Scope to operation Figure 3 8 Trigger Adjustment ...

Page 58: ...ch Clock Ch2 4 2 4 2 Timing Relationship of Driver Card D1 Data Pattern Ch1 and Driver Card D1 Group 1 GTLP Data Out Ch2 4 3 4 3 Timing Relationship of Driver Card D1 Data Pattern Ch1 and Receiver Card R2 Group 1 GTLP Data In Ch2 4 4 4 4 Timing Relationship of Driver Card D1 Data Pattern Ch1 and Receiver Card R2 Group 1 LVTTL Data Out Ch2 4 5 4 5 Timing Relationship of Receiver Card R2 Group 1 GTL...

Page 59: ... D1 Latch Clock Ch2 Figure 4 1 shows the probe hookup and related O Scope output for Case 1 The LVTTL latch clock signal goes to the SN74GTLPH1655 driving device CLK pin and the LVTTL data signal goes to the A port input pin specifically the Group 1 bit 1 data signal Figure 4 1 Case 1 D1 Data Pattern Ch1 and D1 Latch Clock Ch2 LVTTL Data Input LVTTL Latch Clock Input ...

Page 60: ... 2 shows the probe hookup and O Scope output for Case 2 The LVTTL data goes into the SN74GTLPH1655 driving device A port input and the GTLP data comes out of the B port output The driver card GTLP data output comes out after the rising edge of the clock in addition to the CLK to B propagation delay This is why the signals look 180 degrees out of phase Figure 4 2 Case 2 D1 Data Pattern Ch1 and D1 G...

Page 61: ... probe hookup and O Scope output for Case 3 The LVTTL data input goes to the SN74GTLPH1655 driving device A port input and the GTLP data input goes to the SN74GTL1655 receiving device B port in slot 2 These waveforms look similar to those in Figure 4 2 but with slightly more delay caused by the flight time between slots 1 and 2 Figure 4 3 Case 3 D1 Data Pattern Ch1 and R2 Group 1 GTLP Data In Ch2 ...

Page 62: ...using the central system clock i e clock arrives at all daughter cards at the same time the total delay from the LVTTL data input on slot 1 to the LVTTL data output on slot 2 is the sum of one clock cycle 20 ns the setup time on the driver card 9 ns and the propagation delay of the GTLPH1655 CLK to A of about 3 ns The GTLP EVM driver card is set up to transmit sixteen bits of data and then wait ei...

Page 63: ... Figure 4 5 shows the probe hookup and O Scope output for Case 5 You can see the flight time delay between the output of the SN74GTLPH1655 driving device B port in slot 1 and the SN74GTL1655 receiving device B port in slot 20 Total flight time is about 9 ns Figure 4 5 Case 5 R2 Group 1 GTLP Data In Ch1 and R20 Group 1 GTLP Data In Ch2 GTLP Data Input GTLP Data Input Flight Time Delay ...

Page 64: ... there is no reason to extend the GTLP signals past the GTLP device B port output pins on operational daughter cards Figures 4 6 and 4 7 show the difference between waveforms taken directly on the backplane and those taken from the monitor test points under fully loaded conditions at a clock frequency of 23 MHz Waveforms shown in Figures 4 6 and 4 7 are at one half clock frequency or 11 5 MHz and ...

Page 65: ...Monitored Waveforms 4 8 ...

Page 66: ...5 1 Troubleshooting Topic Page 5 1 Spare Parts 5 2 5 2 Replacing 5 A Fuse F2 5 3 5 3 Replacing 2 5 A Fuse F1 5 4 5 4 Damage to the Daughter Cards 5 5 Chapter 5 ...

Page 67: ...Spare Parts 5 2 5 1 Spare Parts Each EVM is equipped with spare fuses and jumpers see Figure 5 1 Figure 5 1 Spare Fuses and Jumpers ...

Page 68: ... is shorted to GND Shorting can occur if a connector pin is bent during insertion or if measurements are taken directly from the backplane F2 can be replaced easily with one of the spare fuses Simply disconnect power from the board and pull out the fuse with pliers see Figure 5 2 Push in the new fuse and reconnect the power supply Figure 5 2 Fuse F2 Left and Removal Procedure Right ...

Page 69: ...s power from the power supply to the 3 3 V and 5 V switching regulators and blows if the switching regulators fail It is replaced as easily as fuse F2 Disconnect the power from the board pull out the fuse with pliers push in the new fuse then reconnect the power supply Figure 5 3 Fuse F1 ...

Page 70: ...Damage to the Daughter Cards 5 5 Troubleshooting 5 4 Damage to the Daughter Cards The daughter cards are not field repairable and must be returned to the factory for repair ...

Page 71: ...Damage to the Daughter Cards 5 6 ...

Page 72: ...A 1 Appendix A Bill of Materials Schematics Board Layouts and Suggested Specifications Topic Page A 1 GTLP EVM Bill of Materials A 2 A 2 Board Layouts and Schematics A 5 Appendix A ...

Page 73: ...Cap 75 Surface Mount Tantalum 10uF 10V Cap 4 Surface Mount Tantalum 1uF 35V Cap 2 Surface Mount Tantalum 47uF 10V Cap 2 Surface Mount 100 ohm Resistor 1 Surface Mount 120 ohm Resistor 1 Surface Mount 1 5K ohm Resistor 1 Surface Mount 20 ohm Resistor 1 Surface Mount 240 ohm Resistor 1 Surface Mount 25 ohm Resistor 1 Green LED 2 Red LED 1 LT1083CP Voltage Regulator 1 Powerjack 1 24V to 5V DC to DC C...

Page 74: ...on Card Device Type Quantity Z PAK 55 Pin Female Connector 1 Surface Mount 0 1uF Cap 4 Surface Mount 25 ohm Resistor 8 Monitored Receiver Card Device Type Quantity Z PAK 55 Pin Female Connector 1 10K ohm Resistor Network 6 SN74ALVC126 TVSOP Buffer 1 SN74GTLP1394 TVSOP Transceiver 1 SN74GTL1655 TSSOP UBT 3 Surface Mount 0 1uF Cap 12 Surface Mount 47pF Cap 6 Surface Mount 1K ohm Resistor 1 Surface M...

Page 75: ...23 Surface Mount 47pF Cap 1 Surface Mount 1K ohm Resistor 3 Surface Mount 2K ohm Resistor 1 Surface Mount 500 ohm Resistor 2 Surface Mount 243 ohm Resistor 1 Surface Mount 51 1 ohm Resistor 6 SMB Coax Connector 8 Unmonitored Receiver Card Device Type Quantity Z PAK 55 Pin Female Connector 1 10K ohm Resistor Network 6 SN74ALVC126 TVSOP Buffer 1 SN74GTLP1394 TVSOP Transceiver 1 SN74GTL1655 TSSOP UBT...

Page 76: ...cs Figure A 1 Backplane Layout Front Side ÇÇ ÇÇ 5 Volts 1 Amp R6 LED 3 P1 17 P1 14 P1 12 P1 7 P1 9 P1 2 JP1 U1 P1 8 LED 2 Group 2 Group 3 LED 1 F2 P1 20 P1 16 P1 13 P1 5 P1 4 P1 1 3 3 Volts 7 5 Amps U2 P1 19 Group 4 Group 1 Group 5 F1 P3 J5 P1 15 P1 10 Group 6 R5 P1 18 P1 11 P1 6 P1 3 Ç Ç Ç Ç U2 R5 and R6 are not installed at this time ...

Page 77: ...Board Layouts and Schematics A 6 Figure A 2 Backplane Layout Back Side ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ P1 20B P1 1B ...

Page 78: ... G3D6 10 11 GND GND GND GND GND 11 GND GND GND GND 15 GND GND GND GND GND 16 G4D3 G4D1 GND G4D4 G4D2 17 G4D7 G4D5 GND G4D8 G4D6 18 GND GND GND GND GND 19 G5D3 G5D1 GND G5D4 G5D2 20 G5D7 G5D5 GND G5D8 G5D6 21 GND GND GND GND GND 22 G6D3 G6D1 GND G6D4 G6D2 23 G6D7 G6D5 GND G6D8 G6D6 24 GND GND GND GND GND 25 MODESEL GND GND GND GTL Clk P3 A B C D E 1 Clk Out 20 GND GND MODESEL 2 Clk Out 18 Clk Out 1...

Page 79: ...Board Layouts and Schematics A 8 Figure A 4 Backplane Schematic ...

Page 80: ...GTLxxx GTLxxx U1 U2 U3 SMB SMB SMB SMB SMB SMB TP1 TP2 TP3 TP4 TP5 TP6 GP1 GP2 GP3 GP4 GP5 GP6 SMB SMB TP8 TP7 CLK DATA ALVCH16344 ALVCH16344 U4 U5 CDC351 U6 LVC112A U7 LVC112A LVC112A U8 U9 ALVC04 U12 PCJ1 GTLP1394 ALVC126 U10 U11 PCJ2 Jumper Block 2 1 2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R13 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C21 C20 R9 C22 2 3 1 R10 Jumper Block ...

Page 81: ...Board Layouts and Schematics A 10 Figure A 6 Driver Card Schematic ...

Page 82: ...cations Figure A 7 Unmonitored Receiver Card Layout 3 5 inches 3 inches OUTPUT Connector AMP type A 100623 1 J1 x column 1 U1 U2 U3 GTL 1655 GTL 1655 GTL 1655 U5 ALVCH126 U4 R1 C1 R2 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 RECEIVER CARD Standard RTerm RTerm RTerm RTerm RTerm RTerm GTLP1394 76 inch C18 ...

Page 83: ... GP6 GP1 GP2 GP3 GP4 GP5 GP6 column 1 U1 U2 U3 GTL 1655 GTL 1655 GTL 1655 U5 ALVCH126 U4 R1 C1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C16 C17 SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB RECEIVER CARD Monitor 10K network 10K network 10K network 10K network 10K network 10K network RTerm RTerm RTerm RTerm RTerm RTerm SMB TP13 CLK GTLP1394 R15 76 in...

Page 84: ...Board Layouts and Schematics A 13 Bill of Materials Schematics Board Layouts and Suggested Specifications Figure A 9 Receiver Card Schematic ...

Page 85: ...ematics A 14 Figure A 10 Clock Card Layout 2 5 inches 2 5 inches OUTPUT Connector CLOCK CLOCK DRIVER SMB Monitor AMP type C 100161 1 CLOCK CARD TP1 U1 U2 R1 J3 C1 C3 C2 C4 C5 CLOCK DRIVER U3 C6 C7 C8 C9 column 1 76 inch C10 ...

Page 86: ...1 12 Vcc 13 GND 3Y3 Vcc GND GND 4Y1 Vcc GND 4Y2 Vcc GND 4Y3 Vcc CLR TEST OE Vcc NC CLKIN Vcc GND FBIN GND SEL0 SEL1 GND CDC2586 GND 1 1Y1 2 Vcc 3 GND 4 1Y2 5 Vcc 6 GND 7 1Y3 8 Vcc 9 GND 10 GND 11 2Y1 12 Vcc 13 GND 14 2Y2 15 Vcc 16 GND 17 2Y3 18 Vcc 19 GND 20 GND 21 3Y1 22 Vcc 23 GND 24 3Y2 25 Vcc 26 GND 27 3Y3 28 Vcc 29 GND 30 GND 31 4Y1 32 Vcc 33 GND 34 4Y2 35 Vcc 36 GND 37 4Y3 38 Vcc 39 CLR 40 T...

Page 87: ...ard Layouts and Schematics A 16 Figure A 12 Resistor Termination Card Layout Output Connector AMP type C 100161 1 column 1 1 5 inch 2 inch R1 R2 R3 R4 R5 R6 R7 R8 C1 C2 C3 C4 J4 Standard termination card ...

Page 88: ...on Card A 1 1 Wednesday December 08 1999 Title Size Document Number Rev Date Sheet of R7 R3 R5 R1 R6 R4 C1 C2 C3 C4 J4 R8 R2 G1 D2 G1 D4 G1 D1 G1 D3 G1 D6 G1 D8 G1 D5 G1 D7 1 5 Z PAK C C1 C2 C3 C4 C5 C6 C7 C8 C9 C1 0 C1 1 D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 0 D1 1 E3E2 E4 E5 E6 E7 E8E9E1 0 E1 1 B1B1 1 E1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A1 0 A1 1 B2 B3 B4 B5 B6 B7 B8 B9 B1 0 ...

Page 89: ...Board Layouts and Schematics A 18 ...

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