c _ REF
5/8
4/9
5/10
1
2
C
R
/ /R
=
´ p ´
´
f
c _ OUT
3/6
2/7
1
2
C
R
=
´ p ´
´
f
c _highpass
4/7
3/8
1
2
C
R
=
´ p ´
´
f
5/10
4/9
5/10
R
OUTA / B
REFA / B
R
R
æ
ö
= ç
÷
+
è
ø
5/10
2/7
2/7
3/8
4/9
5/10
3/8
R
R
R
OUTA / B
INA / B
1
REFA / B
R
R
R
R
æ
ö
æ
öæ
ö
= -
+
+
ç
÷
ç
֍
÷
+
è
ø
è
øè
ø
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Schematic and PCB Layout
9
SBOU193 – July 2017
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Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
Equation 5
displays the dc transfer function of the inverting amplifier circuit configuration.
where
•
C
4/7
is shorted with a 0-
Ω
resistor
(5)
Capacitor C4 for channel A and C7 for channel B provide the option to ac couple the input of the circuit.
Equation 6
displays the dc transfer function of the ac-coupled inverting amplifier circuit configuration.
where
•
The input is ac coupled with C
4/7
(6)
Equation 7
calculates the cut-off frequency of the high-pass filter.
(7)
Capacitors C3 and C6 provide the option to filter the output.
Equation 8
calculates the cut-off frequency of
the filter.
(8)
Capacitor C5 for channel A and C8 for channel B provide the option to filter noise introduced from the
reference voltage, REFA/B.
Equation 9
calculates the cutoff frequency of the filter.
(9)
Figure 12
displays the PCB layout of the top layer of the inverting amplifier circuit configuration.
Figure 12. Inverting Amplifier Top Layer PCB Layout