+
±
V+
C2
V-
C1
R5
C4
VREF
VIN-
R3
R4
VREF
RG
R2
+
±
V+
V-
R1
VOUT
R6
C3
VREF
VIN+
Schematic and PCB Layout
www.ti.com
14
SBOU193 – July 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
Figure 20
displays the PCB layout of the top layer of the Riso with dual-feedback circuit configuration.
Figure 20. Riso With Dual-Feedback PCB Layout
3.8
Two Op-Amp Instrumentation Amplifier
Figure 21
displays the schematic for the two op-amp instrumentation amplifier circuit configuration.
Figure 21. Two Op-Amp Instrumentation Amplifier Schematic
The two op-amp instrumentation amplifier takes a differential input and outputs a single-ended signal. This
circuit configuration provides a high-impedance input to sources interfacing with this circuit. While the two
op-amp instrumentation amplifier does not provide as high of common mode rejection ration (CMRR) as
the three op-amp instrumentation amplifier topology, the two op-amp instrumentation requires only two op
amps, thereby reducing cost.
