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5/13/2014
DRV8846EVM_MSP430F2617_RevA.SchDoc
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DRV8846EVM
Project Title:
Designed for:
Public Release
Assembly Variant:
001
© Tex as Instruments
2014
Drawn By:
Engineer:
Rick Duncan
Te xas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Te xas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Te xas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
Not in version control
SVN Rev:
DRV8846EVM
Number:
Rev:
A
MSP430 w JTAG Interface
USB TO UART
1
2
3
4
5
6
7
10
11
8
9
J6
ZX62-B-5PA(11)
TXD
1
DTR#
2
RTS#
3
VCCIO
4
RXD
5
RI#
6
GND
7
NC
8
DSR#
9
DCD#
10
CTS#
11
CBUS4
12
CBUS2
13
CBUS3
14
USBDP
15
USBDM
16
3V3OUT
17
GND
18
RST#
19
VCC
20
GND
21
CBUS1
22
CBUS0
23
NC
24
AGND
25
TEST
26
OSCI
27
OSCO
28
U3
FT232RL
0.1µF
C9
GND
V3P3
1
2
L1
MI0805K400R-10
GND
GND
R
X
TX
TX
RX
V3P3
DVCC
1
P6.3/A3
2
P6.4/A4
3
P6.5/A5
4
P6.6/A6
5
P6.7/A7/SVSIN
6
VREF+
7
XIN
8
XOUT
9
VEREF+
10
VREF-/VEREF-
11
P1.0/TACLK/CAOUT
12
P1.1/TA0
13
P1.2/TA1
14
P1.3/TA2
15
P1.4/SMCLK
16
P
1
.5
/T
A
0
1
7
P
1
.6
/T
A
1
1
8
P
1
.7
/T
A
2
1
9
P
2
.0
/A
C
L
K
/C
A
2
2
0
P
2
.1
/T
A
IN
C
L
K
/C
A
3
2
1
P
2
.2
/C
A
O
U
T
/T
A
0
/C
A
4
2
2
P
2
.3
/C
A
0
/T
A
1
2
3
P
2
.4
/C
A
1
/T
A
2
2
4
P
2
.5
/R
O
S
C
/C
A
5
2
5
P
2
.6
/A
D
C
1
2
C
L
K
/C
A
6
2
6
P
2
.7
/T
A
0
/C
A
7
2
7
P
3
.0
/U
C
B
0
S
T
E
/U
C
A
0
C
L
K
2
8
P
3
.1
/U
C
B
0
S
IM
O
/U
C
B
0
S
D
2
9
P
3
.2
/U
C
B
0
S
O
M
I/
U
C
B
0
S
C
3
0
P
3
.3
/U
C
B
0
C
L
K
/U
C
A
0
S
T
E
3
1
P
3
.4
/U
C
A
0
T
X
D
/U
C
A
0
S
IM
3
2
P3.5/UCA0RXD
33
P3.6
34
P3.7
35
P4.0/TB0
36
P4.1/TB1
37
P4.2/TB2
38
P4.3
39
P4.4
40
P4.5
41
P4.6
42
P4.7/TBCLK
43
P5.0
44
P5.1
45
P5.2
46
P5.3
47
P5.4/MCLK
48
P
5
.5
/S
M
C
L
K
4
9
P
5
.6
/A
C
L
K
5
0
P
5
.7
/T
B
O
U
T
H
/S
V
S
O
U
T
5
1
X
T
2
O
U
T
5
2
X
T
2
IN
5
3
T
D
O
/T
D
I
5
4
T
D
I/
T
C
L
K
5
5
T
M
S
5
6
T
C
K
5
7
R
S
T
/N
M
I
5
8
P
6
.0
/A
0
5
9
P
6
.1
/A
1
6
0
P
6
.2
/A
2
6
1
A
V
S
S
6
2
D
V
S
S
6
3
A
V
C
C
6
4
U2
MSP430F2617TPMR
GND
GND
GND
R
S
T
V3P3
3.32k
R8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
J5
PEC07DAAN
V3P3
M
S
P
_
D
E
C
0
M
S
P
_
I1
M
S
P
_
I0
M
S
P
_
T
O
F
F
_
S
E
L
M
S
P
_
M
1
M
S
P
_
M
0
GND
FTDI regulator used for 3.3V
STATUS
MSP_VREF
MSP_BVREF
330
R7
GND
S
T
A
T
U
S
GND
R
S
T
C
1
A
2
D2
4
1
3
2
S1
EVQP1D05M
M
S
P
_
C
A
7
M
S
P
_
D
E
C
1
MSP_nFAULT
MSP_nSLEEP
MSP_ADEC
MSP_DIR
MSP_nENBL
MSP_STEP
MSP_VINT
GND
0.1µF
C10
0.1µF
C4
DM
DP
VBUS
0.1µF
C5
4.7µF
C11
0
R10
0
R9
DNP
DNP R9. If debug or
programming adapter is used
to power the MSP430,
remove R10 and populate R9
1µF
C8
GND
Introduction
Figure 3. DRV8846 Schematic (2 of 2)
10
DRV8846 Evaluation Module
SLLU203A – June 2014 – Revised March 2015
Copyright © 2014–2015, Texas Instruments Incorporated
