+
±
Piezo
Elemen t
V
DD
V
(REXT)
R
(S)
V
(Pul ldo wn)
V
HV
C
(HV)
Output
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The second reference voltage is set to about 93% of V
FB
by creating an additional resistor divider in the
feedback network (V
FB2A
and V
FB2B
). This works, such that when the output is rippling during normal
operation, the threshold will not be triggered. However, when the input signal changes so that the output
needs to be discharged, the feedback network will be changed so this reference will become higher than
V
REXT
and therefore turn on the output FET.
Figure 14. Pulldown Network
Figure 15
and
Figure 16
show the different discharge times with and without the pulldown network. Note
the 4x timescale in
Figure 16
.
V
DD
= 5 V
C
(LOAD)
= 22 nF
V
HV
= 0 to 500 V
V
DD
= 5 V
C
(LOAD)
= 22 nF
V
HV
= 0 to 500 V
500us/div
2ms/div
Figure 15. With FET Pulldown
Figure 16. Without FET Pulldown
18
DRV2700EVM-HV500 High Voltage Piezo Driver Evaluation Kit
SLOU407A – April 2015 – Revised May 2015
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