Texas Instruments AFE722 Series, User Manual

Page: 10 / 18

CDCE72010
SMA
Connector
R112 0 S
CLK IN
AFE722x
Clk In
DNI
DNI
BPF DNI
Y0P
Y1P Y1N
SMA
Connector
CDC AUX
IN
AUX
SMA
Connector
REF IN Pri Ref
TCXO
19.2 MHz
Sec Ref
PLL Lock
SMA
Connector
CLK IN-N
DNI
PLL Lock
Y2P
TSW3100
C70 22pF
DNI
C71 22pF
DNI
R74 0 S
R76 0 S
R144
0 S
R72
0 S
R79
0
DNI
S
R81
0
DNI
S
R86 0 S
R161
0
DNI
S
Y2N
AUX IN
x3
/3
/4
CDCE72010
AFE722x
TSW3100
Opt. BPF
Clocking Configuration
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The CDCE72010 clock buffer on the AFE722x is used to provide the clock to the TSW3100. Additional
dividers can be added to the clock output in order to divide the clock appropriately for optional
interpolation by 2x or 4x.
Preconfigured setup files:
AUX IN – INT2x – div3 AFE div8 TSW.txt ext 3x clock to CDC AUX IN (see 6.5)
AUX IN – div3 AFE div4 TSW.txt ext 3x clock to CDC AUX IN (see 6.1)
REF IN (10MHz) – div6 AFE div8 TSW.txt ext 10MHz clock on REF IN (see 6.2)
REF IN (10MHz) – INT2x – div6 AFE div16 TSW.txt ext 10MHz clock on REF IN (see 6.2/6.5)
REF IN (122.88MHz) – div6 AFE div8 TSW.txt ext 122.88MHz clock on REF IN (see 6.2)
6.1 Non-VCXO Option (default)
This setup is the default configuration and provides the
option to operate AFE722x and TSW3100 synchronous at
any arbitrary sampling rate without the use of a VCXO.
This setup is useful for testing the AFE722x at clock
frequencies where a VCXO is not immediately available.
10 EVM Description SLOU330 – December 2011
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