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2
Introduction
3
Analog Interface
3.1
Analog Input – Channel A0
Introduction
The ADS8364 and ADS8365 are high-speed, low-power, 6-channel, 16-bit A/D converters that operate
from indep5-V Avdd and Dvdd supplies. Internal buffer circuits powered from 3.3-V to 5.5-V BVdd
supplies allow for mixed logic level operation without additional level translation.
The six input channels contain fully differential sample-and-hold circuits which are divided into three pairs
(A, B, and C). Each channel pair has a hold signal (HOLDA, HOLDB, and HOLDC) which, when strobed
together, provides simultaneous sampling on all six analog inputs. The devices accept analog input
voltages in the range of –V
REF
to +V
REF
. The parts also accept bipolar input ranges when a level shift
circuit is used in the analog front-end circuitry (see
Figure 1
).
Conversion time for the ADS8364 and ADS8365 is 3.2
µ
s when a 5-MHz external clock is used. The
corresponding acquisition time is 800 ns. To achieve maximum output rate (250 kHz per channel, effective
1.5-MSPS throughput max), the read function can be performed during the start of the next conversion.
The analog input to the EVM is divided in two parts. Connector J4 provides access to input channels A0
and A1 through two different amplifier circuit configurations. The input buffer configuration of channel A0
presents a typical front-end circuit for the A/D converter. Its function is to provide level and impedance
adaptation of the input signal. The input to channel A1 is a bipolar configuration using the INA159 to
accommodate
±
10-V input signals. Connector J3 provides access to the remaining analog input channels
through simple R/C filters.
The analog input to the ADS8364/65MEVM board for channel A0 is composed of the dual OPA2132
operational amplifier and its associated circuitry as shown in
Figure 1
. The OPA2132 is powered from the
±
12-V analog supply, and arranged as an inverting amplifier with a gain of 1. The in2.5-V
reference voltage of the ADS8364 or ADS8365 is applied to the noninverting input of the OPA2132 to
provide input bias.
2
ADS8364/65MEVM
SLAU189 – September 2006
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