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5
Power Supplies
5.1
Reference Voltages
6
EVM Operation
Power Supplies
Table 3. J1 Pinout and Functions
Pin Number
Signal
Description
J1.1
NAP
Controls power-down options on the ADS8365 (only) using the NAP input pin
J1.3
ADD
Controls read options, when HI, address information can be read from the chip
J1.5
HOLD_C#
Active-low signal HOLDC used to start a conversion on ADC channel pair C
J1.7
HOLD_B#
Active-low signal HOLDB used to start a conversion on ADC channel pair B
J1.9
HOLD_A#
Active-low signal HOLDA used to start a conversion on ADC channel pair A
J1.11
RESET#
Active-low signal RESET used to place the ADS7864’s FIFO in reset state
J1.13
NA
Unused on the ADS8364/65MEVM
J1.15
NA
Unused on the ADS8364/65MEVM
J1.17
DC_TOUTa
Used with W10 to allow host processor timer control of HOLDx
J1.19
NA
Unused on the ADS8364/65MEVM
The ADS8364/65MEVM board re5 VDC for the both the analog and digital section of the ADC.
The supply (+Va and +Vd) can range from +4.75 VDC to +5.25 VDC. . The internal buffer can be powered
through the BVdd input voltage and can range from 2.7 VDC to 5.5 VDC. Because the EVM is designed to
work with the 5-6K and HPA-MCU Interface Boards, JP1 provides direct connection to the common power
bus described in
SLAU104
.
Table 4
shows the pinout of JP1:
Table 4. JP1 Pinout
Signal
Pin Number
Signal
+VA (positive input buffer supply)
1
2
-VA (negative input buffer supply)
+5VA (+Va to the ADS8364)
3
4
-5VA (Unused)
DGND
5
6
AGND
+1.8VD (Unused)
7
8
+VD1 (Unused)
+3.3VD (used with W5 for support circuitry)
9
10
+5VD (+5V to pin 22 of the ADS8364 and pin 22 of the
ADS8365)
Alternate power sources can be applied via various test points located on the EVM. See the schematic at
the end of this document for details. Note – while filters are provided for all power supply inputs, optimal
performance of the EVM requires a clean, well-regulated power source.
The ADS8364/65MEVM is configured to use its internal reference through jumper W3 (see schematic for
details). If an external reference is desired, the shunt jumper on W3 should be moved to cover pins 1-2;
the external reference source can be applied to the test point labeled TP10 referenced to TP12. The
in2.5-V reference is still connected to the input buffer U1 in this case to ensure proper mid-point
biasing to channel A1.
The analog input swing is 5 Vpp, centered on a +2.5-V internal or external reference. The installed device
accepts bipolar input ranges when a level shift circuit is used in the analog front-end circuitry. For
information on various circuit configurations, see section 3.2 of this document or section 12 of Op-Amps
for Everyone (
SLOD006
) .
Once power is applied to the EVM, the analog input source can be connected directly to J3 or J4 (top or
bottom side) or through optional amplifier and signal-conditioning modules using the 5-6K and HPA-MCU
Interface Boards. The analog input level should not exceed 5 Vp-p. The analog input range is from
±
Vref
(typically 2.5 VDC) centered at +2.5 V.
6
ADS8364/65MEVM
SLAU189 – September 2006
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