ICLKP
ICLKM
SEN
SDA
SCLOCK
PDWN
SEN
RESET
SCLOCK
+3.3VD
+3.3V
A
+3.3VD
+3.3VD
+3.3VD
+3.3VD
+3.3VD
+3.3VD
IN_M
SH1
IN_P
SH1
D2_D3_P
SH4
D0_D1_P
SH4
D0_D1_M
SH4
D2_D3_M
SH4
D4_D5_P
SH4
D4_D5_M
SH4
D6_D7_P
SH4
D6_D7_M
SH4
ICLKP
SH3
ICLKM
SH3
ADCRESET
SH5
SDA
T
A
SH5
VREF
SH1
PDN
SH5
CS
SH5
SCLK
SH5
FPGA_SEN
SH4
FPGA_SCLK
SH4
FPGA_SDA
T
A
SH4
CLKOUTP
SH4
CLKOUTM
SH4
D8_D9_P
SH4
D8_D9_M
SH4
D10_D1
1_P
SH4
D10_D1
1_M
SH4
D12_D13_P
SH4
D12_D13_M
SH4
PARALLELINTERFACE
SERIALINTERFACE
Default:Shunt2-3
Default:Shunt1-2
Default:Shunt2-3
Default:Shunt2-3
R17
100
R17
100
1
2
R1
1
1K
R1
1
1K
1
2
R10
10K
R10
10K
1
2
TP5TP5
R6
10K
R6
10K
1
2
R20
100
R20
100
1
2
SW1SW1
C13
.1uF
C13
.1uF
1
2
J4J4
2
4
6
8
1
3
5
7
R14
1K
R14
1K
1
2
R8
100
R8
100
1
2
J2J2
1
2
3
U1
ADS614X
U1
ADS614X
DR
VDD
1
RESET
2
SCLK
3
SDA
T
A
4
SEN
5
AGND
6
CLKP
7
CLKM
8
AGN
D
9
IN
P
10
IN
M
11
AGN
D
12
AV
DD
13
CM
_R
EF
IN
14
AV
DD
_F
VD
D
15
PD
N
16
D0_D1_M
17
D0_D1_P
18
D2_D3_M
19
D2_D3_P
20
D4_D5_M
21
D4_D5_P
22
D6_D7_M
23
D6_D7_P
24
CL
KO
UT
M
25
CL
KO
UT
P
26
D8
_D
9_
M
27
D8
_D
9_
P
28
D1
0_
D1
1_
M
29
D1
0_
D1
1_
P
30
D1
2_
D1
3_
M
31
D1
2_
D1
3_
P
32
DR
VSS(GNDP
AD)
33
R64
0OHM
DoNotInstall
R64
0OHM
DoNotInstall
J7J7
1
2
3
TP6TP6
R7
0OHM
R7
0OHM
R9
1K
R9
1K
1
2
R18
10K
R18
10K
1
2
C12
.1uF
C12
.1uF
1
2
TP1TP1
R19
100
R19
100
1
2
R13
100
R13
100
1
2
TP3TP3
TP2TP2
R15
10K
R15
10K
1
2
C85
.1uF
C85
.1uF
1
2
R62
0OHM
DoNotInstall
R62
0OHM
DoNotInstall
J1J1
2
4
6
8
1
3
5
7
J3J3
1
2
3
TP4TP4
C1
1
.1uF
C1
1
.1uF
1
2
J6J6
1
2
3
R3
1K
R3
1K
1
2
R12
100
R12
100
1
2
R5
1K
R5
1K
1
2
J5J5
1
2
3
R63
0OHM
DoNotInstall
R63
0OHM
DoNotInstall
R4
1K
R4
1K
1
2
R16
10
R16
10
Physical Description
www.ti.com
Figure 8. EVM Schematic, Sheet 2
24
SLAU206B – September 2007 – Revised April 2008
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