D12_D13_P
SH2
D12_D13_M
SH2
D10_D11_P
SH2
D10_D11_M
SH2
D8_D9_P
SH2
D8_D9_M
SH2
CLKOUTP
SH2
CLKOUTM
SH2
D6_D7_P
SH2
D6_D7_M
SH2
D4_D5_P
SH2
D4_D5_M
SH2
D2_D3_P
SH2
D2_D3_M
SH2
D0_D1_P
SH2
D0_D1_M
SH2
CDC_CLKP
SH3
CDC_CLKM
SH3
FPGA_SCLK
SH2
FPGA_SEN
SH2
FPGA_SDATA SH2
J10
CONN_QTH_30X2-D-A
J10
CONN_QTH_30X2-D-A
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
G1
G2
G3
G4
G5
G6
G7
G8
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Physical Description
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Figure 10. EVM Schematic, Sheet 4
26
SLAU206B – September 2007 – Revised April 2008
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