Texas Instruments ADS5XJ6XEVM, User Manual, Page: 16 / 22

Appendix A
SLAU641D – June 2015 – Revised January 2016
A.1 Jumper Descriptions
Table 7 shows the EVM jumpers and the default settings for the jumpers. Use this table to reset the EVM
in the default configuration in case of issues.
Table 7. Jumper Descriptions and Default Settings
Jumper Description Default setting
SW1 ADC hardware reset (active high) Logic low
JP2 Power enable to VCXO oscillator Y1. Default is power on. Shunt pins 1-2
JP3 Selects SPI source from USB or FMC. Default is USB. Shunt pins 2-3
JP7 ADC power down. Default is ADC powered on. Shunt pins 2-3
SJP1 Selects either 3.3 V or GND for Y1 enable. Default is open Open
A.2 Connector Descriptions
The EVM connectors and their function described in Table 8 .
Table 8. Connector Description
Connector Description
J1 Channel A analog input
J17 Channel B analog input
J18 Channel C analog input
J5 Channel D analog input
J6 External ADC sample clock input
J10 LMK04828 external sync input
J12 LMK04828 reference clock input
J3 JESD204B FMC connector. Interfaces to TSW14J56EVM or FPGA evaluation
boards.
J13 (USB) USB interface connector
J14 (+5V IN) 5-V power supply input
J15 (JTAG) JTAG interface to CPLD
J21 TRDYAB test point (pin1) and GND (pin 2). Manual burst mode trigger input.
J22 TRDYCD test point (pin1) and GND (pin 2). Trigger ready output for burst mode.
J23 TRIGAB test point (pin1) and GND (pin 2). Manual burst mode trigger input.
J24 TRIGCD test point (pin1) and GND (pin 2). Trigger ready output for burst mode.
16 SLAU641D – June 2015 – Revised January 2016
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