Teridian 73S1209F Datasheet Download | Manualshive

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DS_1209F_004

73S1209F Data Sheet

Rev. 1.2

83

V

CC

Stable Timer Register (VccTmr): 0xFE04

Å

0x0F

A programmable timer is provided to set the time from activation start (setting the VCCSEL.1 and
VCCSEL.0 bits to non-zero) to when VCC_OK is evaluated. VCC_OK must be true at the end of this
timers programmed interval (tto in

Figure 15

) in order for the activation sequence to continue. If VCC_OK

is not true and the end of the interval (tto), the Card Event interrupt will be set, and a deactivation
sequence shall begin including clearing of the VCCSEL bits.

Table 77: The VccTmr Register

MSB

LSB

OFFTMR.3 OFFTMR.2 OFFTMR.1 OFFTMR.0 VCCTMR.3 VCCTMR.2 VCCTMR.1 VCCTMR.0

Bit Symbol

Function

VccTmr.7 OFFTMR.3

VCC Off Timer – The bits set the delay (in number of ETUs) for
deactivation after the VCCSEL.1 and VCC SEL.0 have been set to 0. The
time value is a count of the 32768Hz clock and is given by tto =
OFFTMR(7:4) * 30.5

μ

s. This delay does not affect emergency

deactivations due to VDD Fault or card events. A value of 0000 results in
no additional delay.

VccTmr.6 OFFTMR.2
VccTmr.5 OFFTMR.1

VccTmr.4 OFFTMR.0

VccTmr.3 VCCTMR.3

VCC Timer – VCCOK must be true at the time set by the value in these
bits in order for the activation sequence to continue. If not, the VCCSEL
bits will be cleared. The time value is a count of the 32768Hz clock and is
given by tto = VCCTMR(3:0) * 30.5

μ

s. A value of 0000 results in no

timeout, not zero time, and activation requires that RDYST is set and RDY
goes high.

VccTmr.2 VCCTMR.2
VccTmr.1 VCCTMR.1

VccTmr.0 VCCTMR.0

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Summary of Contents for 73S1209F

Page 1: ...M Alternatively to the turnkey firmware offered by Teridian customers can develop their own embedded firmware directly within their application or using Teridian 73S1209F Evaluation Board through a JTAG like interface Overall the Teridian 73S1209F IC requires 2 distinct power supply voltages to operate normally with full support of all smart card voltages 1 8V 3V and 5V The digital power supply VD...

Page 2: ... for transmit and receive Configured to drive multiple external Teridian 73S8010x interfaces for multi SAM architectures Communication Interfaces Full duplex serial interface 1200bps to 115kbps UART I2 C Master Interface 400kbps Man Machine Interface and I Os 5x6 Keyboard hardware scanning debouncing and scrambling 9 User I Os Up to 2 programmable current outputs LED Voltage Detection Analog Input...

Page 3: ... 46 1 7 7 User USR Ports 49 1 7 8 Analog Voltage Comparator 51 1 7 9 LED Drivers 53 1 7 10 I2 C Master Interface 54 1 7 11 Keypad Interface 61 1 7 12 Emulator Port 67 1 7 13 Smart Card Interface Function 68 1 7 14 VDD Fault Detect Function 102 2 Typical Application Schematics 103 3 Electrical Specification 105 3 1 Absolute Maximum Ratings 105 3 2 Recommended Operating Conditions 105 3 3 Digital IO...

Page 4: ...ing ATR Signals 76 Figure 21 Creation of Synchronous Clock Start Stop Mode Start Bit in Sync Mode 77 Figure 22 Creation of Synchronous Clock Start Stop Mode Stop Bit in Sync Mode 77 Figure 23 Operation of 9 bit Mode in Sync Mode 78 Figure 24 73S1209F Typical PINpad Smart Card Reader Application Schematic 103 Figure 25 73S1209F Typical SIM Smart Card Reader Application Schematic 104 Figure 26 12 MH...

Page 5: ...er 36 Table 25 External MPU Interrupts 36 Table 26 Control Bits for External Interrupts 37 Table 27 Priority Level Groups 37 Table 28 The IP0 Register 37 Table 29 The IP1 Register 38 Table 30 Priority Levels 38 Table 31 Interrupt Polling Sequence 38 Table 32 Interrupt Vectors 38 Table 33 UART Modes 39 Table 34 Baud Rate Generation 39 Table 35 The PCON Register 40 Table 36 The BRCON Register 40 Tab...

Page 6: ...ster 86 Table 82 The SRXData Register 87 Table 83 The SCCtl Register 88 Table 84 The SCECtl Register 89 Table 85 The SCDIR Register 90 Table 86 The SPrtcol Register 91 Table 87 The SCCLK Register 92 Table 88 The SCECLK Register 92 Table 89 The SParCtl Register 93 Table 90 The SByteCtl Register 94 Table 91 The FDReg Register 95 Table 92 Divider Ratios Provided by the ETU Counter 95 Table 93 Divider...

Page 7: ...FLASH INTERFACE TEST OCDSI ISR WATCH DOG TIMER PMU PORTS TIMER_0_ 1 MEMORY_ CONTROL CONTROL UNIT RAM_ SFR_ CONTROL ALU RESET VOLTAGE REFERENCE AND FUSE TRIM CIRCUITRY VPD REGULATOR ANA_IN PLL and TIMEBASES VDD SCRATCH IRAM 256B 12MHz OSCILLATOR X12OUT X12IN COL4 COL3 COL2 COL1 COL0 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0 KEYPAD INTERFACE I2 C MASTER INT SDA SCL USR 8 0 DRIVERS USR7 USR6 USR5 USR4 USR3 USR1 ...

Page 8: ...onfigurable as inputs or outputs or as external input interrupt ports SCL 5 5 O Figure 28 I2 C master mode compatible Clock signal Note the pin is configured as an open drain output When the I2C interface is being used an external pull up resistor is required A value of 3K is recommended SDA 6 6 IO Figure 27 I2 C master mode compatible data I O Note this pin is bi directional When the pin is confi...

Page 9: ...gnal IO 63 42 IO Figure 38 Smart card Data IO signal AUX1 62 41 IO Figure 38 Auxiliary Smart Card IO signal C4 AUX2 61 40 IO Figure 38 Auxiliary Smart Card IO signal C8 VCC 60 39 PSO Smart Card VCC supply voltage output A 0 47μF capacitor is required and should be located at the smart card connector The capacitor should be a ceramic type with low ESR GND 58 37 GND Smart Card Ground VPC 55 34 PSI S...

Page 10: ... is an on chip regulator that uses VDD to provide power for internal circuits VPD A 0 1μF capacitor is recommended at each VDD pin N C 2 4 7 8 26 27 39 46 16 17 29 No connect GND 9 25 44 7 15 GND General ground supply pins for all IO and logic circuits RESET 66 1 I Figure 31 Reset input positive assertion Resets logic and registers to default condition See the figures in the Equivalent Circuits se...

Page 11: ...ian s standard library A standard ANSI C 80515 application programming interface library is available to help reduce design cycle Refer to the 73S12xxF Software User s Guide 1 3 2 Memory Organization The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces Memory organization in the 80515 is similar to that of the industry standard 8051 There are three memory are...

Page 12: ... of the flash memory address such that bit 7 1 of the PGADDR corresponds to bit 15 9 of the flash memory address Bit 0 of the PGADDR is not used and is ignored The MPU may write to the flash memory This is one of the non volatile storage options available to the user The FLSHCTL SFR bit FLSH_PWE flash program write enable differentiates 80515 data store instructions MOVX DPTR A between Flash and X...

Page 13: ...the flash memory page address page 0 through 127 that will be erased during the Page Erase cycle default 0x00 Note the page address is shifted left by one bit see detailed description above Must be re written for each new Page Erase cycle FLSHCTL 0xB2 R W Bit 0 FLSH_PWE Program Write Enable 0 MOVX commands refer to XRAM Space normal operation default 1 MOVX DPTR A moves A to Program Space Flash DP...

Page 14: ...ternal Data Memory Map Address Direct Addressing Indirect Addressing 0xFF Special Function Registers SFRs RAM 0x80 0x7F Byte addressable area 0x30 0x2F Byte or bit addressable area 0x20 0x1F Register banks R0 R7 x4 0x00 External Data Memory While the 80515 can address up to 64KB of external data memory in the space from 0x0000 to 0xFFFF only the memory ranges shown in Figure 2 contain physical mem...

Page 15: ...2 Memory Map Dual Data Pointer The Dual Data Pointer accelerates the block moves of data The standard DPTR is a 16 bit register that is used to address external memory In the 80515 core the standard data pointer is called DPTR the second data pointer is called DPTR1 The data pointer select bit chooses the active pointer The data pointer select bit is located at the LSB of the DPS IRAM special func...

Page 16: ... XRAM SFR register SECReg 0xFFD7 fuse must be blown beforehand or the security mode 0 will not be enabled The SECSET0 and SECSET1 fuses once blown cannot be overridden Specifically when SECURE is set The ICE is limited to bulk flash erase only Page zero of flash memory may not be page erased by either MPU or ICE Page zero may only be erased with global flash erase Note that global flash erase eras...

Page 17: ... prevent external reading of flash memory and CE program RAM This bit is reset on chip reset and may only be set Attempts to write zero are ignored TRIMPCtl 0xFFD1 W 0xA6 value will cause the selected fuse to be blown All other values will stop the burning process FUSECtl 0xFFD2 W 0x54 value will set up for security fuse control All other values are reserved and should not be used SECReg 0xFFD7 W ...

Page 18: ...CAN KSTAT KSIZE KORDERL KORDERH D7 C8 T2CON CF C0 IRCON C7 B8 IEN1 IP1 S0RELH S1RELH BF B0 FLSHCTL PGADDR B7 A8 IEN0 IP0 S0RELL AF A0 USR8 UDIR8 A7 98 S0CON S0BUF IEN2 S1CON S1BUF S1RELL 9F 90 USR70 UDIR70 DPS ERASE 97 88 TCON TMOD TL0 TL1 TH0 TH1 MCLKCtl 8F 80 SP DPL DPH DPL1 DPH1 WDTREL PCON 87 Only a few addresses are used the others are not implemented SFRs specific to the 73S1209F are shown i...

Page 19: ...User Port Data 7 0 UDIR70 0x91 0xFF User Port Direction 7 0 DPS 0x92 0x00 Data Pointer select Register ERASE 0x94 0x00 Flash Erase S0CON 0x98 0x00 Serial Port 0 Control Register S0BUF 0x99 0x00 Serial Port 0 Data Buffer IEN2 0x9A 0x00 Interrupt Enable Register 2 S1CON 0x9B 0x00 Serial Port 1 Control Register S1BUF 0x9C 0x00 Serial Port 1 Data Buffer S1RELL 0x9D 0x00 Serial Port 1 Reload Register l...

Page 20: ...OW 0XD2 0x3F Keypad Row KSCAN 0XD3 0x00 Keypad Scan Time KSTAT 0XD4 0x00 Keypad Control Status KSIZE 0XD5 0x00 Keypad Size KORDERL 0XD6 0x00 Keypad Column LS Scan Order KORDERH 0XD7 0x00 Keypad Column MS Scan Order BRCON 0xD8 0x00 Baud Rate Control Register only BRCON 7 bit used A 0xE0 0x00 Accumulator B 0xF0 0x00 B Register 20 Rev 1 2 ...

Page 21: ...0x FF92 0x00 External Interrupt Control 3 USRIntCtl4 0x FF93 0x00 External Interrupt Control 4 INT5Ctl 0x FF94 0x00 External Interrupt Control 5 INT6Ctl 0x FF95 0x00 External Interrupt Control 6 MPUCKCtl 0x FFA1 0x0C MPU Clock Control ACOMP 0x FFD0 0x00 Analog Compare Register TRIMPCtl 0x FFD1 0x00 TRIM Pulse Control FUSECtl 0x FFD2 0x00 FUSE Control VDDFCtl 0x FFD4 0x00 VDDFault Control SECReg 0x...

Page 22: ...n at location 0x08 Data Pointer The data pointer DPTR is 2 bytes wide The lower part is DPL and the highest is DPH It can be loaded as a 2 byte register MOV DPTR data16 or as two registers e g MOV DPL data8 It is generally used to access external code or data space e g MOVC A A DPTR or MOVX A DPTR respectively Program Counter The program counter PC is 2 bytes wide initialized to 0x0000 after reset...

Page 23: ...these ports if they are not used for alternate purposes 1 6 Instruction Set All instructions of the generic 8051 microcontroller are supported A complete list of the instruction set and of the associated op codes is contained in the 73S12xxF Software User s Guide 1 7 Peripheral Descriptions 1 7 1 Oscillator and Clock Generation The 73S1209F has a single oscillator circuit for the main CPU clock Th...

Page 24: ...EL ETU CLOCK DIVIDER 12 bits CPUCKDiv See SC Clock descriptions for more accurate diagram ETUCLK MCount 2 0 KEYCLK I2CCLK 1kHz 400kHz DIVIDE by 120 DIVIDER 93760 HIGH XTAL OSC X12IN X12OUT M DIVIDER 2 N 4 HCLK HOSCen 12 00MHz 12 00MHz div 2 ICLK SCCKenb SELSC DIVIDE by 96 CLK1M 1MHz 7 386MHz 7 386MHz 3 6923MHz I2C_2x 800kHz div 2 SCECLK div 2 div 2 Figure 3 Clock Generation and Control Circuits 24...

Page 25: ...8 00 4 6 86 5 6 00 6 Master Clock Control Register MCLKCtl 0x8F Å 0x0A Table 12 The MCLKCtl Register MSB LSB HSOEN KBEN SCEN MCT 2 MCT 1 MCT 0 Bit Symbol Function MCLKCtl 7 HSOEN High speed oscillator disable When set 1 disables the high speed crystal oscillator and VCO PLL system Do not set this bit 1 MCLKCtl 6 KBEN 1 Disable the keypad logic clock MCLKCtl 5 SCEN 1 Disable the smart card logic cl...

Page 26: ... 6923MHz MPUCKCtl 4 MDIV 4 MPUCKCtl 3 MDIV 3 MPUCKCtl 2 MDIV 2 MPUCKCtl 1 MDIV 1 MPUCKCtl 0 MDIV 0 The oscillator circuits are designed to connect directly to standard parallel resonant crystal in a Pierce oscillator configuration Each side of the crystal should include a 22pF capacitor to ground for both oscillator circuits and a 1MΩ resistor is required across the 12MHz crystal The CPU clock is ...

Page 27: ...e PWRDN Signal is not the direct version of the PWRDN Bit There are delays from assertion of the PWRDN bit to the assertion of the PWRDN Signal 32 MPU clocks Refer to the Power Down sequence diagram Flash Read Pulse one shot circuit MISCtl1 FRPEN Figure 5 Power Down Control When the PWRDN bit is set the clock subsystem will provide a delay of 32 MPUCLK cycles to allow the program to set the STOP b...

Page 28: ...DN BIT PWRDN SIG EXT EVENT INT0 to MPU MPU STOP ANALOG Enable PLL CLOCKS t1 t2 t3 t4 t5 t6 t0 t7 t0 MPU sets PWRDN bit t1 32 MPU clock cycles after t0 the PWRDN SIG is asserted turning all analog functions OFF t2 MPU executes STOP instruction must be done prior to t1 t3 Analog functions go to OFF condition No Vref PLL VCO Ibias etc text text An external event RTC Keypad Card event USB occurs t4 PW...

Page 29: ...0 when this register is read INT5Ctl 6 INT5Ctl 5 INT5Ctl 4 INT5Ctl 3 INT5Ctl 2 INT5Ctl 1 KPIEN Keypad interrupt enable INT5Ctl 0 KPINT Keypad interrupt flag Miscellaneous Control Register 0 MISCtl0 0xFFF1 Å 0x00 Table 15 The MISCtl0 Register MSB LSB PWRDN SLPBK SSEL Bit Symbol Function MISCtl0 7 PWRDN This bit sets the circuit into a low power condition All analog high speed oscillator and VCO PLL...

Page 30: ...er MSB LSB HSOEN KBEN SCEN MCT 2 MCT 1 MCT 0 Bit Symbol Function MCLKCtl 7 HSOEN High speed oscillator enable When set 1 disables the high speed crystal oscillator and VCO PLL system This bit is not changed when the PWRDN bit is set but the oscillator VCO PLL is disabled MCLKCtl 6 KBEN 1 Disable the keypad logic clock This bit is not changed in PWRDN mode but the function is disabled MCLKCtl 5 SCE...

Page 31: ...te generator is setup via this register Table 18 The PCON Register MSB LSB SMOD GF1 GF0 STOP IDLE Bit Symbol Function PCON 7 SMOD If SM0D 1 the baud rate is doubled PCON 6 PCON 5 PCON 4 PCON 3 GF1 General purpose flag 1 PCON 2 GF0 General purpose flag 1 PCON 1 STOP Sets CPU to Stop mode PCON 0 IDLE Sets CPU to Idle mode ...

Page 32: ...e signals that originate in other parts of the 73S1209F for example the USR I O smart card interface analog comparators etc The external interrupt configuration is shown in Figure 8 External interrupts are the interrupts external to the 80515 core i e signals that originate in other parts of the 73S1209F for example the USR I O smart card interface analog comparators etc The external interrupt con...

Page 33: ... interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector address Interrupt response will require a varying amount of time depending on the state of the MPU when the interrupt occurs If the MPU is performing an interrupt service with equal or greater priority the new interrupt will not be invoked In other cases the response time depends on the current instruction The f...

Page 34: ...rol IEN1 5 EX6 EX6 0 disable external interrupt 6 IEN1 4 EX5 EX5 0 disable external interrupt 5 IEN1 3 EX4 EX4 0 disable external interrupt 4 IEN1 2 EX3 EX3 0 disable external interrupt 3 IEN1 1 EX2 EX2 0 disable external interrupt 2 IEN1 0 Interrupt Enable 2 Register IEN2 0x9A Å 0x00 Table 21 The IEN2 Register MSB LSB ES1 Bit Symbol Function IEN2 0 ES1 ES1 0 disable serial channel interrupt 34 Re...

Page 35: ...se an interrupt TCON 1 IE0 Interrupt 0 edge flag is set by hardware when the falling edge on external interrupt int0 is observed Cleared when an interrupt is processed TCON 0 IT0 Interrupt 0 type control bit 1 selects falling edge and 0 sets low level for input pin to cause interrupt Timer Interrupt 2 Control Register T2CON 0xC8 Å 0x00 Table 23 The T2CON Register MSB LSB I3FR I2FR Bit Symbol Funct...

Page 36: ...n subsequent sections Generic 80515 MPU literature states that interrupts 4 through 6 are defined as rising edge sensitive Thus the hardware signals attached to interrupts 4 5 and 6 are converted to rising edge level by the hardware SFR special function register enable bits must be set to permit any of these interrupts to occur Likewise each interrupt has its own flag bit that is set by the interr...

Page 37: ...ture All interrupt sources are combined in groups as shown in Table 27 Table 27 Priority Level Groups Group 0 External interrupt 0 Serial channel 1 interrupt 1 Timer 0 interrupt External interrupt 2 2 External interrupt 1 External interrupt 3 3 Timer 1 interrupt External interrupt 4 4 Serial channel 0 interrupt External interrupt 5 5 External interrupt 6 Each group of interrupt sources can be prog...

Page 38: ...nterrupt External interrupt 4 External interrupt 5 External interrupt 6 1 7 3 6 Interrupt Sources and Vectors Table 32 shows the interrupts with their associated flags and vector addresses Table 32 Interrupt Vectors Interrupt Request Flag Description Interrupt Vector Address N A Chip Reset 0x0000 IE0 External interrupt 0 0x0003 TF0 Timer 0 interrupt 0x000B IE1 External interrupt 1 0x0013 TF1 Timer...

Page 39: ...34 shows how the baud rates are calculated Table 33 UART Modes UART 0 UART 1 Mode 0 N A Start bit 8 data bits parity stop bit variable baud rate internal baud rate generator Mode 1 Start bit 8 data bits stop bit variable baud rate internal baud rate generator or timer 1 Start bit 8 data bits stop bit variable baud rate internal baud rate generator Mode 2 Start bit 8 data bits parity stop bit fixed...

Page 40: ...N 3 GF1 General purpose flag 1 PCON 2 GF0 General purpose flag 1 PCON 1 STOP Sets CPU to Stop mode PCON 0 IDLE Sets CPU to Idle mode Baud Rate Control Register 0 BRCON 0xD8 Å 0x00 The BSEL bit used to enable the baud rate generator is set up via this register Table 36 The BRCON Register MSB LSB BSEL Bit Symbol Function BRCON 7 BSEL If BSEL 0 the baud rate is derived using timer 1 If BSEL 1 the bau...

Page 41: ...d in Mode 0 by setting the flags in S0CON as follows RI0 0 and REN0 1 In other modes a start bit when REN0 1 starts receiving serial data Mode 1 Pin RX serves as input and TX serves as serial output No external shift clock is used 10 bits are transmitted a start bit always 0 8 data bits LSB first and a stop bit always 1 On receive a start bit synchronizes the transmission 8 data bits are available...

Page 42: ...ardware after completion of a serial reception Must be cleared by software 1 7 4 2 Serial Interface 1 The Serial Interface 1 can operate in 2 modes Mode A This mode is similar to Mode 2 and 3 of Serial interface 0 11 bits are transmitted or received a start bit 0 8 data bits LSB first a programmable 9th bit and a stop bit 1 The 9th bit can be used to control the parity of the serial interface at t...

Page 43: ...flag set by hardware after completion of a serial transfer Must be cleared by software S1CON 0 RI1 Receive interrupt flag set by hardware after completion of a serial reception Must be cleared by software Multiprocessor operation mode The feature of receiving 9 bits in Modes 2 and 3 of Serial Interface 0 or in Mode A of Serial Interface 1 can be used for multiprocessor communication In this case t...

Page 44: ... the appropriate mode The Timer 0 load registers are designated as TL0 and TH0 and the Timer 1 load registers are designated as TL1 and TH1 Timer Counter Mode Control Register TMOD 0x89 Å 0x00 Table 40 The TMOD Register MSB LSB GATE C T M1 M0 GATE C T M1 M0 Timer 1 Timer 0 Bits TR1 and TR0 in the TCON register start their associated timers when set Table 41 TMOD Register Bit Description Bit Symbol...

Page 45: ...upper 3 bits of TL0 are indeterminate and should be ignored Setting the run flag TRx does not clear the registers Mode 0 operation is the same for timer 0 as for timer 1 Mode 1 Mode 1 is the same as mode 0 except that the timer register is run with all 16 bits Mode 2 Mode 2 configures the timer register as an 8 bit counter TLx with automatic reload The overflow from TLx not only sets TFx but also ...

Page 46: ...er a reset the watchdog timer is disabled and all registers are set to zero The watchdog consists of a 16 bit counter WDT a reload register WDTREL prescalers by 2 and by 16 and control logic Once the watchdog starts it cannot be stopped unless the internal reset signal becomes active WD Timer Start Procedure The WDT is started by setting the SWDT flag When the WDT register enters the state 0x7CFF ...

Page 47: ...flow interrupt IEN0 2 EX1 EX1 0 disable external interrupt 1 IEN0 1 ET0 ET0 0 disable timer 0 overflow interrupt IEN0 0 EX0 EX0 0 disable external interrupt 0 Interrupt Enable 1 Register IEN1 0xB8 Å 0x00 Table 45 The IEN1 Register MSB LSB SWDT EX6 EX5 EX4 EX3 EX2 Bit Symbol Function IEN1 7 IEN1 6 SWDT Watchdog timer start refresh flag Set to activate refresh the watchdog timer When directly set af...

Page 48: ... and respond accordingly Can be read and cleared by software Note The remaining bits in the IP0 register are not used for watchdog control Watchdog Timer Reload Register WDTREL 0x86 Å 0x00 Table 47 The WDTREL Register MSB LSB WDPSEL WDREL6 WDREL5 WDREL4 WDREL3 WDREL2 WDREL1 WDREL0 Bit Symbol Function WDTREL 7 WDPSEL Prescaler select bit When set the watchdog is clocked through an additional divide...

Page 49: ...r VDD Table 48 Direction Registers and Internal Resources for DIO Pin Groups USR Pin Group Type Direction Register Name Direction Register SFR Location Data Register Name Data Register SFR Location USR_0 USR_7 Multi use UDIR70 0x91 7 0 USR70 0x90 7 0 USR_8 GPIO only UDIR8 0xA1 0 USR8 0xA0 0 Table 49 UDIR Control Bit UDIR Bit 0 1 USR Pin Function output input Four XRAM SFR registers USRIntCtl1 USRI...

Page 50: ...ter USRIntCtl2 0xFF91 Å 0x00 Table 52 The USRIntCtl2 Register MSB LSB U3IS 6 U3IS 5 U3IS 4 U2IS 2 U2IS 1 U2IS 0 External Interrupt Control Register USRIntCtl3 0xFF92 Å 0x00 Table 53 The USRIntCtl3 Register MSB LSB U5IS 6 U5IS 5 U5IS 4 U4IS 2 U4IS 1 U4IS 0 External Interrupt Control Register USRIntCtl4 0xFF93 Å 0x00 Table 54 The USRIntCtl4 Register MSB LSB U7IS 6 U7IS 5 U7IS 4 U6IS 2 U6IS 1 U6IS 0 ...

Page 51: ...D0 Å 0x00 Table 55 The ACOMP Register MSB LSB ANALVL ONCHG CPOL CMPEN TSEL 2 TSEL 1 TSEL 0 Bit Symbol Function ACOMP 7 ANALVL When read indicates whether the input level is above or below the threshold This is a real time value and is not latched so it may change from the time of the interrupt trigger until read ACOMP 6 ACOMP 5 ONCHG If set the Ana_interrupt is invoked on any change above or below...

Page 52: ... enable INT6Ctl 4 VFTINT VDD fault interrupt flag INT6Ctl 3 I2CIEN I2 C interrupt enabled INT6Ctl 2 I2CINT I2 C interrupt flag INT6Ctl 1 ANIEN If ANIEN 1 Analog Compare event interrupt is enabled When masked ANIEN 0 ANINT bit 0 may be set but no interrupt is generated INT6Ctl 0 ANINT Read Only Set when the selected ANA_IN signal changes with respect to the selected threshold if Compare_Enable is a...

Page 53: ...rent The pins may be used as inputs with consideration of the programmed output current and level The register bit when read indicates the state of the pin LED Control Register LEDCtl 0xFFF3 Å 0xFF Table 57 The LEDCtl Register MSB LSB LPUEN ISET 1 ISET 0 LEDD 1 LEDD0 Bit Symbol Function LEDCtl 7 LEDCtl 6 LPUEN 0 Pull ups are enabled for all of the LED pins LEDCtl 5 ISET 1 These two bits control th...

Page 54: ...when a subsequent I2 C transaction is started The I2 C interface uses a 400kHz clock from the time base circuits 1 7 10 1 I2 C Write Sequence To write data on the I2 C Master Bus the 80515 has to program the following registers according to the following sequence 1 Write slave device address to Device Address register DAR The data contains 7 bits for the slave device address and 1 bit of op code T...

Page 55: ...read data on the I2 C Master Bus from a slave device the 80515 has to program the following registers in this sequence 1 Write slave device address to Device Address register DAR The data contains 7 bits device address and 1 bit of op code The op code bit should be written with a 1 2 Write control data to Control and Status register CSR Write a 1 to bit 1 to start I2 C Master Bus Also write a 1 to...

Page 56: ...B LSB MSB Device Address 7 0 Read Data 7 0 I2c_Interrupt Start I2C CSR bit1 Transfer length CSR bit0 1 7 8 9 10 17 18 ACK bit No ACK bit STOP condition START condition SCL SDA LSB MSB LSB MSB Device Address 7 0 Read Data 7 0 I2c_Interrupt Start I2C CSR bit1 Transfer length CSR bit0 Secondary Read Data 7 0 ACK bit 19 26 27 Figure 10 I2 C Read Operation 56 Rev 1 2 ...

Page 57: ...ymbol Function DAR 7 DVADR 0 6 Slave device address DAR 6 DAR 5 DAR 4 DAR 3 DAR 2 DAR 1 DAR 0 I2CRW If set 0 the transaction is a write operation If set 1 read I2C Write Data Register WDR 0XFF81 Å 0x00 Table 59 The WDR Register MSB LSB WDR 7 WDR 6 WDR 5 WDR 4 WDR 3 WDR 2 WDR 1 WDR 0 Bit Function WDR 7 Data to be written to the I2 C slave device WDR 6 WDR 5 WDR 4 WDR 3 WDR 2 WDR 1 WDR 0 ...

Page 58: ...econd Data byte to be written to the I2 C slave device if bit 0 I2CLEN of the Control and Status register CSR is set 1 SWDR 6 SWDR 5 SWDR 4 SWDR 3 SWDR 2 SWDR 1 SWDR 0 I2C Read Data Register RDR 0XFF83 Å 0x00 Table 61 The RDR Register MSB LSB RDR 7 RDR 6 RDR 5 RDR 4 RDR 3 RDR 2 RDR 1 RDR 0 Bit Function RDR 7 Data read from the I2 C slave device RDR 6 RDR 5 RDR 4 RDR 3 RDR 2 RDR 1 RDR 0 58 Rev 1 2 ...

Page 59: ...SR 0xFF85 Å 0x00 Table 63 The CSR Register MSB LSB AKERR I2CST I2CLEN Bit Symbol Function CSR 7 CSR 6 CSR 5 CSR 4 CSR 3 CSR 2 AKERR Set to 1 if acknowledge bit from Slave Device is not 0 Automatically reset when the new bus transaction is started CSR 1 I2CST Write a 1 to start I2 C transaction Automatically reset to 0 when the bus transaction is done This bit should be treated as a busy indicator ...

Page 60: ...n INT6Ctl 7 INT6Ctl 6 INT6Ctl 5 VFTIEN VDD fault interrupt enable INT6Ctl 4 VFTINT VDD fault interrupt flag INT6Ctl 3 I2CIEN When set 1 the I2 C interrupt is enabled INT6Ctl 2 I2CINT When set 1 the I2 C transaction has completed Cleared upon the start of a subsequent I2 C transaction INT6Ctl 1 ANIEN Analog compare interrupt enable INT6Ctl 0 ANINT Analog compare interrupt flag 60 Rev 1 2 ...

Page 61: ... 1 0 7 6 5 4 3 2 1 0 KSTAT Register Keypad Clock Keypad Clock VDD pull up COL4 0 ROW5 0 73S1209F If smaller keypad than 6 x 5 is to be implemented unused row inputs should be connected to VDD Unused column outputs should be left unconnected VDD Figure 11 Simplified Keypad Block Diagram There are 5 drive lines outputs corresponding to columns and 6 sense lines inputs corresponding to rows Hysteresi...

Page 62: ...is scanned If only one key is pressed a valid key is detected Simultaneous key presses are not considered as valid If two keys are pressed no key is reported to firmware Possible scrambling of the column scan order is provided by means of KORDERL and KORDERH registers that define the order of column scanning Values in these registers must be updated every time a new keyboard scan order is desired ...

Page 63: ...e key s still released No No KSCAN Register Debouncing Time KSTAT Register Enable HW Scanning Enable Keypad Interrupt Keypad Scanning KORDERL H Registers Column Scan Order KSTAT Register Key Detect Interrupt Yes KCOL Register Value of the valid key column KROW Register Value of the valid key row KSCAN Register Scanning Rate KSIZE Register Keypad Size Definition 0 key Register Used to Control the h...

Page 64: ...x0F COL 4 low all others high 0x1F COL 4 0 all high KCOL 3 COL 3 KCOL 2 COL 2 KCOL 1 COL 1 KCOL 0 COL 0 Keypad Row Register KROW 0xD2 Å 0x3F This register contains the value of the row of a key detected as valid by the hardware In bypass mode this register firmware reads directly this register to carry out manual detection Table 66 The KROW Register MSB LSB ROW 5 ROW 4 ROW 3 ROW 2 ROW 1 ROW 0 Bit ...

Page 65: ...CEN KEYDET KYDTEN Bit Symbol Function KSTAT 7 KSTAT 6 KSTAT 5 KSTAT 4 KSTAT 3 KEYCLK The current state of the keyboard clock can be read from this bit KSTAT 2 HWSCEN Hardware Scan Enable When set the hardware will perform automatic key scanning When cleared the firmware must perform the key scanning manually bypass mode KSTAT 1 KEYDET Key Detect When HWSCEN 1 this bit is set causing an interrupt t...

Page 66: ...s grouped into 5 sets of 3 bits each Each set determines which column COL 4 0 pin to activate by loading the column number into the 3 bits When in HW_Scan_Enable mode the hardware will step through the sets from 1Col to 5Col up to the number of columns in Colsize and scan the column defined in the 3 bits To scan in sequential order set a counting pattern with 0 in set 0 and 1 in set 1 and 2 in set...

Page 67: ...et 1 indicates interrupt from Real Time Clock function Cleared on read of register INT5Ctl 3 USBIEN USB interrupt enable INT5Ctl 2 USBINT USB interrupt flag INT5Ctl 1 KPIEN Enables Keypad interrupt when set 1 INT5Ctl 0 KPINT This bit indicates the Keypad logic has set Key_Detect bit and a key location may be read Cleared on read of register 1 7 12 Emulator Port The emulator port consisting of the ...

Page 68: ...tl SParCtl Card Interrupt Management SCInt SCIE External ICC Interface Bypass Mode XRAM Registers VccCtl VccTMR SCCLK SCSCLK Timers 2 Byte Tx FIFO 2 Byte Rx FIFO Card and Mode Selection TX RX SCDir SCECtl BGT0 1 2 3 CWT0 1 SIO SCLK SCCLK SCSCLK Figure 13 Smart Card Interface Block Diagram Figure 13 Smart Card Interface Block Diagram Card interrupts are managed through two dedicated registers SCIE ...

Page 69: ...6 3 and EMV4 0 standards This converter requires a separate 5 0V input supply source designated as VPC Auxiliary I O lines C4 and C8 are only provided for the built in interface If support for the auxiliary lines is necessary for the externa n the I O SIO and clock SCLK signals and control is handled via the I2 C interface Figure 14 shows how multiple 8010 devices can be connected to the 73S1209F ...

Page 70: ...ol assuming 12MHz crystal with various F D settings Firmware manages F D All F D combinations are supported in which F D is directly divisible by 31 or 32 i e F D is a multiple of either 31 or 32 Flexible ETU clock generation and control Detection of convention direct or indirect character TS This affects both polarity and order of bits in byte Convention can be overridden by firmware Supports WTX...

Page 71: ...tected the hardware will automatically perform the deactivation sequence and then generate an interrupt to the firmware The firmware can then perform any other error handling required for proper system operation Smart card RST I O and CLK C4 C8 shall be low before the end of the deactivation sequence Figure 16 shows the timing for a deactivation sequence VCCSEL bits VCC VCCOK bit RSTCRD bit RST CL...

Page 72: ...PPS negotiation between the smart card and the reader the firmware may determine that the smart card parameters F D may be changed After this negotiation the firmware may change the ETU by writing to the SFR FDReg to adjust the ETU and CLK The firmware may also change the smart card clock frequency by writing to the SFR SCCLK SCECLK for external interface Independent clock frequency control is pro...

Page 73: ...via an interrupt During transmission of a message the firmware will write bytes into the transmit FIFO The hardware will send them to the smart card When the last byte of a message has been written the firmware will need to set the LASTTX bit in the STXCtl SFR This will cause the hardware to insert the CRC LRC if in a T 1 protocol mode CRC LRC generation checking is only provided during T 1 proces...

Page 74: ...smart card UART in order for the firmware to support non T 0 T 1 smart cards This is called Bypass mode In this mode the embedded firmware will communicate directly with the selected smart card and drive I O during transmit and read I O during receive in order to communicate with the smart card In this mode ATR processing is under firmware control The firmware must sequence the interface signals a...

Page 75: ...functions such as I O source selection I O signal bypasses the FIFOs and is controlled by the SCCLK SCECLK SFRs When the RLen counter reaches the max loaded value it sets the WAITTO interrupt SEInt bit 7 which is maskable via WTOIEN SCIE bit 7 It must be reloaded in order to start the counting clocking process again This allows the processor to select the number of CLK cycles and hence the number ...

Page 76: ...mpled on the rising edge of CLK IO changes on the falling edge of CLK either from the card or from the 73S1209F The RST signal to the card is directly controlled by the RSTCRD bit non inverted via the MPU and is shown as an example of a possible RST pattern Figure 19 Synchronous Activation IO reception on RST CLK CLKOFF CLKLVL Rlength Interrupt RLength Count RLenght 1 TX RXB Mode bit TX 1 1 Clear ...

Page 77: ...rtion in Synchronous mode for Synchronous Clock Start Stop Mode protocol RLen 0 Rlen 1 2 1 3 7 6 5 6 4 Figure 21 Creation of Synchronous Clock Start Stop Mode Start Bit in Sync Mode RLength Count Rlength 9 CLK IO RLength Interrupt CLK Stop CLK Stop Level IO Bit IODir Bit TX RX Mode Bit TX 1 I2CMode 1 Data to from Card I2CMode 0 Data from TX fifo I2CMode 1 ACK Bit to from card I2CMode 0 Data from T...

Page 78: ...rupt CLK CLK Stop CLK Stop Level 0 1 _ Interrupt generated when Rlength counter is Max 2 _Stop CLK after the last byte and protection bit Stop CLK after receiving the last byte and protection bit Receive data in 9 bit mode Figure 23 Operation of 9 bit Mode in Sync Mode Synchronous card operation is broken down into three primary types These are commonly referred to as 2 wire 3 wire and I2C synchro...

Page 79: ...3S8010x devices can be connected to the external smart card interface Table 73 The SCSel Register MSB LSB SELSC 1 SELSC 0 BYPASS Bit Symbol Function SCSel 7 SCSel 6 SCSel 5 SCSel 4 SCSel 3 SELSC 1 Select Smart Card Interface These bits select the interface that is using the IS0 UART These bits do not activate the interface Activation is performed by the VccCtl register 00 No smart card interface s...

Page 80: ...VCC Timer This bit is set when the VCCTMR times out This bit is cleared when the SCInt register is read SCInt 4 RXDAV Rx Data Available Data was received from the smart card because the Rx FIFO is not empty In bypass mode this interrupt is generated on a falling edge of the smart card I O line After receiving this interrupt in bypass mode firmware should disable it until the firmware has received ...

Page 81: ... the MPU Table 75 The SCIE Register MSB LSB WTOIEN CDEVEN VTMREN RXDAEN TXEVEN TXSNTEN TXEREN RXEREN Bit Symbol Function SCIE 7 WTOIEN Wait Timeout Interrupt Enable Enable for ATR or Wait Timeout Interrupt In sync mode function is RLIEN RLen max interrupt enable SCIE 6 CDEVEN Card Event Interrupt Enable SCIE 5 VTMREN VCC Timer Interrupt Enable SCIE 4 RXDAEN Rx Data Available Interrupt Enable SCIE ...

Page 82: ... 5V A card event or VCCOK going low will initiate a deactivation sequence When the deactivation sequence for RST CLK and I O is complete VCC will be turned off When this type of deactivation occurs the bits must be reset before initiating another activation VccCtl 6 VCCSEL 0 VccCtl 5 VDDFLT If this bit is set 0 the CMDVCC3B and CMDVCC5B outputs are immediately set 1 to signal to the companion circ...

Page 83: ... Symbol Function VccTmr 7 OFFTMR 3 VCC Off Timer The bits set the delay in number of ETUs for deactivation after the VCCSEL 1 and VCC SEL 0 have been set to 0 The time value is a count of the 32768Hz clock and is given by tto OFFTMR 7 4 30 5μs This delay does not affect emergency deactivations due to VDD Fault or card events A value of 0000 results in no additional delay VccTmr 6 OFFTMR 2 VccTmr 5...

Page 84: ... de bounce function shall wait for 64ms of stable card detect assertion before setting the CARDIN bit This counter timer uses the keypad clock as a source of 1kHz signal De assertion of the CARDIN bit is immediate upon de assertion of the card detect pin s CRDCtl 6 CDETEN Card Detect Enable When set 1 activates card detection input Default upon power on reset is 0 CRDCtl 5 CRDCtl 4 CRDCtl 3 DETPOL...

Page 85: ...terrupt upon going empty STXCtl 3 TXUNDR TX Underrrun Read only Asserted when a transmit under run condition has occurred An under run condition is defined as an empty TX FIFO when the last data word has been successfully transmitted to the smart card and the LASTTX bit was not set No special processing is performed by the hardware if this condition occurs Cleared when read by firmware This bit ge...

Page 86: ...hat was sampled on the ninth CLK or SCLK rising edge This is used to read data in synchronous 9 bit formats SRXCtl 6 SRXCtl 5 LASTRX Last RX Byte User sets this bit during the reception of the last byte When byte is received and this bit is set logic checks CRC to match 0x1D0F T 1 mode or LRC to match 00h T 1 mode otherwise a CRC or LRC error is asserted SRXCtl 4 CRCERR Read only 1 CRC or LRC erro...

Page 87: ...gister MSB LSB SRXDAT 7 SRXDAT 6 SRXDAT 5 SRXDAT 4 SRXDAT 3 SRXDAT 2 SRXDAT 1 SRXDAT 0 Bit Function SRXData 7 Read only Data received from the smart card Data received from the smart card gets stored in a FIFO that is read by the firmware SRXData 6 SRXData 5 SRXData 4 SRXData 3 SRXData 2 SRXData 1 SRXData 0 ...

Page 88: ... on the latest rising edge of CLK SCCtl 4 IOD Smart Card I O Direction control Bypass mode or sync mode 1 input default 0 output SCCtl 3 C8 Smart Card C8 When C8 is an output the value written to this bit will appear on the C8 line The value read when C8 is an output is the value stored in the register When C8 is an input the value read is the value on the C8 pin Caution this signal is not synchro...

Page 89: ... necessary Table 84 The SCECtl Register MSB LSB SIO SIOD SCLKLVL SCLKOFF Bit Symbol Function SCECtl 7 SCECtl 6 SCECtl 5 SIO External Smart Card I O Bit when read indicates state of pin SIO for SIOD 1 Caution this signal is not synchronized to the MPU clock when written sets state of pin SIO for SIOD 0 Ignored if not in bypass or sync modes In sync mode this bit will contain the value of IO pin on ...

Page 90: ...irection of the internal interface C4 C8 lines After reset all signals are tri stated Table 85 The SCDIR Register MSB LSB C8D C4D Bit Symbol Function SCDIR 7 SCDIR 6 SCDIR 5 SCDIR 4 SCDIR 3 C8D 1 input 0 output Smart Card C8 direction SCDIR 2 C4D 1 input 0 output Smart Card C4 direction SCDIR 1 SCDIR 0 90 Rev 1 2 ...

Page 91: ...ard External Synchronous mode Configures External Smart Card interface for synchronous mode This mode routes the external smart card interface buffers for SIO to SCECtl register bits for direct firmware control SCLK is generated by the ETU counter SPrtcol 4 0 Reserved bit must always be set to 0 SPrtcol 3 TMODE Protocol mode select 0 T 0 1 T 1 Determines which smart card protocol is to be used dur...

Page 92: ...register value 1 SCCLK 4 ICLKFS 4 SCCLK 3 ICLKFS 3 SCCLK 2 ICLKFS 2 SCCLK 1 ICLKFS 1 SCCLK 0 ICLKFS 0 External SC Clock Configuration Register SCECLK 0xFE10 Å 0x0C This register controls the external smart card SCLK clock generation Table 88 The SCECLK Register MSB LSB ECLKFS 5 ECLKFS 4 ECLKFS 3 ECLKFS 2 ECLKFS 1 ECLKFS 0 Bit Symbol Function SCECLK 7 SCECLK 6 SCECLK 5 ECLKFS 5 External Smart Card ...

Page 93: ...abled This also applies to TS during ATR SParCtl 4 BRKDET Break Detection Disable 1 disabled 0 enabled If enabled and T 0 protocol the UART will detect the generation of a Break by the smart card SParCtl 3 RETRAN Retransmit Byte 1 enabled 0 disabled If enabled and a Break is detected from the smart card Break Detection must be enabled the last character will be transmitted again This bit applies t...

Page 94: ...TS by the smart card to the firmware The hardware will check parity and generate a break as defined by the DISPAR and BRKGEN bits in the parity control register This bit is cleared by hardware after TS is received TS is decoded before being stored in the receive FIFO SByteCtl 5 DIRTS Direct Mode TS Select 1 direct mode 0 indirect mode Set cleared by hardware when TS is processed indicating either ...

Page 95: ... high frequency intermediate signal MSCLK by 2 The ETU baud rate is created by dividing MSCLK by 2 times the Fi Di ratio specified by the codes below For example if FI 0001 and DI 0001 the ratio of Fi Di is 372 1 Thus the ETU divider is configured to divide by 2 372 744 The maximum supported F D ratio is 4096 Table 92 Divider Ratios Provided by the ETU Counter FI code 0000 0001 0010 0011 0100 0101...

Page 96: ...8 186 279 372 1000 12 62 62 93 124 186 248 0101 16 47 47 70 93 140 186 1001 20 37 37 56 74 112 149 0110 32 23 23 35 47 70 93 Fi code 0110 1001 1010 1011 1100 1101 Di code F D 1860 512 768 1024 1536 2048 0001 1 3720 1024 1536 2048 3072 4096 0010 2 1860 512 768 1024 1536 2048 0011 4 930 256 384 512 768 1024 0100 8 465 128 192 256 384 512 1000 12 310 85 128 171 256 341 0101 16 233 64 96 128 192 256 1...

Page 97: ...15 8 are undefined During LRC CRC checking and generation this register is updated with the current value and can be read to aid in debugging This information will be transmitted to the smart card using the timing specified by the Guard Time register When checking CRC LRC on an incoming message CRC LRC is checked against the data and CRC LRC the firmware reads the final value after the message has...

Page 98: ...T 8 Most significant bit for 9 bit EGT timer See EGT below BGT 6 BGT 5 BGT 4 BGT 4 Time in ETUs between the start bit of the last received character to start bit of the first character transmitted to the smart card Default value is 22 BGT 3 BGT 3 BGT 2 BGT 2 BGT 1 BGT 1 BGT 0 BGT 0 Extra Guard Time Register EGT 0xFE17 Å 0x0C This register contains the Extra Guard Time Value EGT least significant b...

Page 99: ...e work wait time is defined as the time between the leading edge of two consecutive characters being sent to or from the card If a timeout occurs an interrupt is generated to the firmware The firmware can then take appropriate action A Wait Time Extension WTX is supported with the 28 bit BWT Character Wait Time Registers CWTB0 0xFE1D Å 0x00 CWTB1 0xFE1C Å 0x00 Table 102 The CWTB0 Register MSB LSB ...

Page 100: ...TS character in the ATR when DETTS is set The timer is started when smart card reset is de asserted An ATR timeout is generated if this time is exceeded MUTE card Reset Time Register RLength 0xFE22 Å 0x70 MSB LSB RLen 7 RLen 6 RLen 5 RLen 4 RLen 3 RLen 1 RLen 2 RLen 0 Table 107 The RLength Register Time in ETUs that the hardware delays the de assertion of RST If set to zero and RSTCRD 0 the hardwa...

Page 101: ... RXB BREAKD STXData FE07 TXDATA 7 0 SRXCtl FE08 BIT9DAT LASTRX CRCERR RXFULL RXEMTY RXOVRR PARITYE SRXData FE09 RXDATA 7 0 SCCtl FE0A RSTCRD IO IOD C8 C4 CLKLVL CLKOFF SCECtl FE0B SIO SIOD SCLKLVL SCLKOFF SCDIR FE0C C8D C4D SPrtcol FE0D I2CMODE MOD9 8B SCESYN 0 TMODE CRCEN CRCMS RCVATR SCCLK FE0F ICLKFS 5 0 SCECLK FE10 ECLKFS 5 0 SParCtl FE11 DISPAR BRKGEN BRKDET RTRAN DISCRX INSPE FORCPE SByteCtl...

Page 102: ...LTEN STXDAT 3 VDDFTH 2 VDDFTH 1 VDDFTH 0 Bit Symbol Function VDDFCtl 7 VDDFCtl 6 FOVRVDDF Setting this bit high will allow the VDDFLT 2 0 bits set in this register to control the VDDFault threshold When this bit is set low the VDDFault threshold will be set to the factory default setting of 2 3V VDDFCtl 5 VDDFLTEN Set 1 will disable VDD Fault operation VDDFCtl 4 VDDFCtl 3 VDDFCtl 2 VDDFTH 2 VDD Fa...

Page 103: ...C1 28 C1 25 C2 1 C2 3 T1IN 24 T2IN 23 T3IN 22 T4IN 19 T5IN 17 R1OUTBF 16 R1OUT 21 R2OUT 20 R3OUT 18 GND 2 MBAUD 15 SHDNB 14 ENB 13 R3IN 11 R2IN 9 R1IN 8 T1OUT 5 T2OUT 6 T3OUT 7 T4OUT 10 T5OUT 12 V 4 V 27 VCC 26 U1 MAX3237CAI SERIAL PORT 1 3 S1 SW_MOM Rev 1 4 103 USR4 USR2 USR1 USR0 USR3 USR5 USR6 C12 27p 1 3 S2 SW_MOM 1 3 S3 SW_MOM 1 3 S4 SW_MOM 1 3 S5 SW_MOM C11 27p R2 10k 1 3 S7 SW_MOM 3 3V 1 3 ...

Page 104: ...10 T5OUT 12 V 4 V 27 VCC 26 U4 MAX3237CAI SERIAL PORT Y2 12 000MHz R6 1M C30 10uF D4 D3 C26 10uF R10 20K LED0 3 LED1 4 SCL 5 SDA 6 GND 7 X12IN 8 X12OUT 9 ANAIN 10 RXD 11 TXD 12 USR7 13 USR6 14 GND 15 NC 16 NC 17 VDD 18 USR5 19 USR4 20 USR3 21 USR2 22 USR1 23 USR0 24 ERST 25 TCLK 26 VDD 27 RXTX 28 NC 29 SCLK 30 SIO 31 INT2 32 TEST 33 RESET 1 SEC 2 VPC 34 PRESB 35 CLK 36 GND 37 RST 38 VCC 39 AUX2 40...

Page 105: ... VDD 0 5 VDC Pin Voltage card interface 0 3 to VCC 0 5 VDC ESD tolerance except card interface 2KV ESD tolerance card interface 6KV Pin Current 200 mA Note ESD testing on smart card pins is HBM condition 3 pulses each polarity referenced to ground Note Smart Card pins are protected against shorts between any combinations of Smart Card pins 3 2 Recommended Operating Conditions Unless otherwise note...

Page 106: ...led Vout VDD 0 1v 5 μA Symbol Parameter Conditions Min Typ Max Unit Iled LED drive current Vout 1 3V 2 7v VDD 3 6v 2 4 10 mA Iolkrow Keypad Row output low current 0 0v Voh 0 1v when pull up R is enabled 100 μA Iolkcol Keypad column output high current 0 0v Voh 0 1v when col is pulled low 3 mA 3 4 Oscillator Interface Requirements Symbol Parameter Condition Min Typ Max Unit High Frequency Oscillato...

Page 107: ...ak ICC 200mA t 400ns 5V 4 6 5 25 V Active mode current pulses of 40nAs with peak ICC 200mA t 400ns 5V 4 65 5 25 V Active mode current pulses of 40nAs with peak ICC 200mA t 400ns 3V 2 7 3 15 V Active mode current pulses of 20nAs with peak ICC 100mA t 400ns 1 8V 1 62 1 92 V VCCrip VCC Ripple fRIPPLE 20kHz 200MHz 350 mV ICCmax Card supply output current Static load current VCC 1 65 40 mA Static load ...

Page 108: ...through 33Ω 15 mA ISHORTH Short circuit output current For output high shorted to ground through 33Ω 15 mA tR tF Output rise time fall times For I O AUX1 AUX2 CL 80pF 10 to 90 100 ns tIR tIF Input rise fall times 1 μs RPU Internal pull up resistor Output stable for 200ns 8 11 14 kΩ FDMAX Maximum data rate 1 MHz Reset and Clock for Card Interface RST CLK VOH Output level high IOH 200μA 0 9 VCC VCC ...

Page 109: ...ly Current VCC on ICC 0 I O AUX1 AUX2 high CLK not toggling 450 650 μA Power down 1 10 IPCOFF VPC supply current when VCC 0 Smart card deactivated 345 μA 3 8 Voltage Temperature Fault Detection Circuits Symbol Parameter Condition Min Typ Max Unit VPCF VPC fault VPC Voltage supervisor threshold VPC VCC a transient event VCC VPC 0 3 V VCCF VCCOK 0 VCC Voltage supervisor threshold VCC 5V 4 6 V VCC 3V...

Page 110: ...4 110 Rev 1 2 4 Equivalent Circuits VDD X12LIN X12OUT ENABLE TTL To circuit ESD ESD Figure 26 12 MHz Oscillator Circuit PIN VDD STRONG PFET STRONG NFET Data From circuit TTL To circuit Output Disable ESD Figure 27 Digital I O Circuit ...

Page 111: ...D STRONG PFET STRONG NFET Data From circuit Output Disable ESD Figure 28 Digital Output Circuit PIN VDD STRONG PFET STRONG NFET Data From circuit TTL To circuit Output Disable Pull up Disable VERY WEAK PFET ESD Figure 29 Digital I O with Pull Up Circuit ...

Page 112: ...004 112 Rev 1 2 PIN VDD STRONG PFET STRONG NFET Data From circuit TTL To circuit Output Disable VERY WEAK NFET Pull down Enable ESD Figure 30 Digital I O with Pull Down Circuit PIN TTL To circuit ESD Figure 31 Digital Input Circuit ...

Page 113: ...STRONG PFET STRONG NFET Data From circuit TTL To circuit Output Disable Pull up Disable 100k OHM ESD Figure 32 Keypad Row Circuit PIN VDD MEDIUM PFET STRONG NFET Data From circuit TTL To circuit Output Disable ESD 1200 OHMS Figure 33 Keypad Column Circuit ...

Page 114: ...TRONG PFET STRONG NFET Data From circuit TTL To circuit Pullup Disable 0 2 4 10mA Current Value Control ESD Figure 34 LED Circuit PIN Vih 0 7 VDD To Circuit Logic R 20kΩ This buffer has a special input threshold ESD Figure 35 Test and Security Pin Circuit ...

Page 115: ...DS_1209F_004 73S1209F Data Sheet Rev 1 2 115 PIN To Comparator Input ESD Figure 36 Analog Input Circuit PIN VCC STRONG PFET STRONG NFET From circuit ESD ESD Figure 37 Smart Card Output Circuit ...

Page 116: ... PFET STRONG NFET RL 11K From circuit CMOS To circuit ESD ESD Figure 38 Smart Card I O Circuit PIN TTL To circuit VERY WEAK NFET Pull down Enable ESD ESD VDD Figure 39 PRES Input Circuit PIN TTL To circuit VERY WEAK PFET Pull up Enable ESD ESD VDD Figure 40 PRES Input Circuit ...

Page 117: ...EST VPC PRESB CLK GND RST VCC AUX2 AUX1 IO PRES VDD RESET SEC ISBR LED0 LED1 SCL SDA N C N C GND XI2IN X12OUT COL0 COL1 COL2 ANA_IN COL3 RXD TXD INT3 SIO TBUS1 SCLK TBUS2 N C RXTX GND TBUS3 VDD TCLK ERST N C ROW5 ROW4 USR0 N C N C USR8 INT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 51 50 49 48 47 ...

Page 118: ...ve component TERIDIAN 73S1209F USR1 USR2 USR3 USR4 USR5 VDD N C N C GND USR6 USR7 TEST VPC PRESB CLK GND RST VCC AUX2 AUX1 IO PRES VDD RESET SEC LED0 SCL SDA GND XI2IN X12OUT ANA_IN RXD TXD SIO SCLK N C RXTX VDD ERST USR0 LED1 INT2 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 12 13 14 15 16 17 33 32 31 30 29 28 27 26 25 24 23 TCLK 44 43 42 41 40 39 38 37 36 35 34 Figure 42 73S1209F Pinout ...

Page 119: ...m Notes 6 3mm x 6 3mm exposed pad area must remain UNCONNECTED clear of PCB traces or vias Controlling dimensions are in mm TOP VIEW TOP VIEW SEATING PLANE 12 SIDE VIEW 68 1 2 3 8 00 7 75 8 00 7 75 0 00 0 05 0 2 0 85 0 65 TERMINAL TIP FOR ODD TERMINAL SIDE L C C C 0 40 SCALE NONE SECTION C C 0 20 0 15 0 25 0 00 0 05 BOTTOM VIEW 68 PIN 1 ID R0 20 0 45 8 00 8 00 6 30 6 15 6 45 0 42 0 24 0 60 0 42 0 ...

Page 120: ...rolling dimensions are in mm TOP VIEW SEATING PLANE 12 SIDE VIEW 44 1 2 3 7 00 6 75 7 00 6 75 0 00 0 05 0 2 0 85 0 65 TERMINAL TIP FOR ODD TERMINAL SIDE L C C C 0 50 SCALE NONE SECTION C C 0 23 0 18 0 30 0 00 0 05 BOTTOM VIEW 44 PIN 1 ID R0 20 0 45 7 00 7 00 5 10 4 95 5 25 0 42 0 24 0 60 0 42 0 24 0 60 5 00 5 00 5 10 4 95 5 25 1 2 3 Figure 44 73S1209F 44 QFN Pinout ...

Page 121: ...9F44IM 6 Related Documentation The following 73S1209F documents are available from Teridian Semiconductor Corporation 73S1209F Data Sheet this document 73S1209F Development Board Quick Start Guide 73S1209F Software Development Kit Quick Start Guide 73S1209F Evaluation Board User s Guide 73S12xxF Software User s Guide 73S12xxF Synchronous Card Design Application Note 7 Contact Information For more ...

Page 122: ...s 1 2 12 16 2008 In Table 1 added more description to the SCL SDA PRES PRESB VCC VPC SEC TEST and VDD pins In Section 1 3 2 changed FLSH_ERASE to ERASE and FLSH_PGADR to PGADDR Added The PGADDR register denotes the page address for page erase The page size is 512 200h bytes and there are 128 pages within the flash memory The PGADDR denotes the upper seven bits of the flash memory address such that...

Page 123: ... In Section 3 4 changed the Fxtal Min value from 4 to 6 Added Section 6 Related Documentation Added Section 7 Contact Information Formatted the document per new standard Added section numbering 2008 Teridian Semiconductor Corporation All rights reserved Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation Windows is a registered trademark of Microsoft ...

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